Author: Benjamin Kramer Date: 2020-01-14T14:06:37+01:00 New Revision: df186507e1d07c3ddba091a076ba7a33dbdc5867
URL: https://github.com/llvm/llvm-project/commit/df186507e1d07c3ddba091a076ba7a33dbdc5867 DIFF: https://github.com/llvm/llvm-project/commit/df186507e1d07c3ddba091a076ba7a33dbdc5867.diff LOG: Make helper functions static or move them into anonymous namespaces. NFC. Added: Modified: clang/lib/AST/ASTImporter.cpp clang/lib/CodeGen/CGBuiltin.cpp clang/lib/CodeGen/CGOpenMPRuntime.cpp clang/lib/Driver/ToolChains/Arch/ARM.cpp clang/lib/StaticAnalyzer/Checkers/CheckPlacementNew.cpp clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp llvm/lib/CodeGen/MIRParser/MIParser.cpp llvm/lib/Target/AArch64/AArch64FrameLowering.cpp llvm/lib/Target/Mips/MipsLegalizerInfo.cpp llvm/lib/Transforms/InstCombine/InstructionCombining.cpp mlir/lib/Analysis/AffineAnalysis.cpp mlir/lib/Analysis/AffineStructures.cpp mlir/lib/Analysis/Liveness.cpp mlir/lib/Analysis/Utils.cpp mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp mlir/lib/Dialect/AffineOps/AffineOps.cpp mlir/lib/Dialect/GPU/IR/GPUDialect.cpp mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp mlir/lib/Dialect/Linalg/Transforms/LinalgToLoops.cpp mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp mlir/lib/Dialect/LoopOps/LoopOps.cpp mlir/lib/Dialect/QuantOps/Transforms/ConvertSimQuant.cpp mlir/lib/Dialect/SDBM/SDBMExpr.cpp mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp mlir/lib/Dialect/SPIRV/Serialization/TranslateRegistration.cpp mlir/lib/Dialect/VectorOps/VectorOps.cpp mlir/lib/Dialect/VectorOps/VectorTransforms.cpp mlir/lib/ExecutionEngine/ExecutionEngine.cpp mlir/lib/IR/SymbolTable.cpp mlir/lib/Pass/PassStatistics.cpp mlir/lib/Transforms/Utils/LoopUtils.cpp mlir/test/lib/TestDialect/TestPatterns.cpp Removed: ################################################################################ diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp index f6c3aa1a3c1d..8eb58b32ae17 100644 --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -3081,7 +3081,7 @@ Error ASTNodeImporter::ImportFunctionDeclBody(FunctionDecl *FromFD, // Returns true if the given D has a DeclContext up to the TranslationUnitDecl // which is equal to the given DC. -bool isAncestorDeclContextOf(const DeclContext *DC, const Decl *D) { +static bool isAncestorDeclContextOf(const DeclContext *DC, const Decl *D) { const DeclContext *DCi = D->getDeclContext(); while (DCi != D->getTranslationUnitDecl()) { if (DCi == DC) diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 7b2b0336c32a..09fd3087b494 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -14260,6 +14260,7 @@ CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID, const CallExpr *E) { } } +namespace { struct BuiltinAlignArgs { llvm::Value *Src = nullptr; llvm::Type *SrcType = nullptr; @@ -14288,6 +14289,7 @@ struct BuiltinAlignArgs { Mask = CGF.Builder.CreateSub(Alignment, One, "mask"); } }; +} // namespace /// Generate (x & (y-1)) == 0. RValue CodeGenFunction::EmitBuiltinIsAligned(const CallExpr *E) { diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index 0d96c5a2f73f..97b17799a03e 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -1438,6 +1438,7 @@ CGOpenMPRuntime::getUserDefinedReduction(const OMPDeclareReductionDecl *D) { return UDRMap.lookup(D); } +namespace { // Temporary RAII solution to perform a push/pop stack event on the OpenMP IR // Builder if one is present. struct PushAndPopStackRAII { @@ -1481,6 +1482,7 @@ struct PushAndPopStackRAII { } llvm::OpenMPIRBuilder *OMPBuilder; }; +} // namespace static llvm::Function *emitParallelOrTeamsOutlinedFunction( CodeGenModule &CGM, const OMPExecutableDirective &D, const CapturedStmt *CS, @@ -11122,8 +11124,8 @@ bool checkContext<OMP_CTX_SET_device, OMP_CTX_kind, CodeGenModule &>( return true; } -bool matchesContext(CodeGenModule &CGM, - const CompleteOMPContextSelectorData &ContextData) { +static bool matchesContext(CodeGenModule &CGM, + const CompleteOMPContextSelectorData &ContextData) { for (const OMPContextSelectorData &Data : ContextData) { switch (Data.Ctx) { case OMP_CTX_vendor: diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp b/clang/lib/Driver/ToolChains/Arch/ARM.cpp index ae1d7eaf7089..a1923e731489 100644 --- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp +++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp @@ -63,9 +63,9 @@ static void getARMHWDivFeatures(const Driver &D, const Arg *A, } // Handle -mfpu=. -unsigned getARMFPUFeatures(const Driver &D, const Arg *A, - const ArgList &Args, StringRef FPU, - std::vector<StringRef> &Features) { +static unsigned getARMFPUFeatures(const Driver &D, const Arg *A, + const ArgList &Args, StringRef FPU, + std::vector<StringRef> &Features) { unsigned FPUID = llvm::ARM::parseFPU(FPU); if (!llvm::ARM::getFPUFeatures(FPUID, Features)) D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args); diff --git a/clang/lib/StaticAnalyzer/Checkers/CheckPlacementNew.cpp b/clang/lib/StaticAnalyzer/Checkers/CheckPlacementNew.cpp index 6fe3cb63cde9..48fee4a0ffb7 100644 --- a/clang/lib/StaticAnalyzer/Checkers/CheckPlacementNew.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/CheckPlacementNew.cpp @@ -6,6 +6,7 @@ using namespace clang; using namespace ento; +namespace { class PlacementNewChecker : public Checker<check::PreStmt<CXXNewExpr>> { public: void checkPreStmt(const CXXNewExpr *NE, CheckerContext &C) const; @@ -22,6 +23,7 @@ class PlacementNewChecker : public Checker<check::PreStmt<CXXNewExpr>> { BugType BT{this, "Insufficient storage for placement new", categories::MemoryError}; }; +} // namespace SVal PlacementNewChecker::getExtentSizeOfPlace(const Expr *Place, ProgramStateRef State, diff --git a/clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp index 861dfef02393..3c04983df443 100644 --- a/clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp @@ -223,7 +223,8 @@ static const ExplodedNode *getAcquireSite(const ExplodedNode *N, SymbolRef Sym, /// Returns the symbols extracted from the argument or null if it cannot be /// found. -SymbolRef getFuchsiaHandleSymbol(QualType QT, SVal Arg, ProgramStateRef State) { +static SymbolRef getFuchsiaHandleSymbol(QualType QT, SVal Arg, + ProgramStateRef State) { int PtrToHandleLevel = 0; while (QT->isAnyPointerType() || QT->isReferenceType()) { ++PtrToHandleLevel; diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 63ed91d67190..076ca943788b 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -1734,8 +1734,8 @@ static bool getHexUint(const MIToken &Token, APInt &Result) { return false; } -bool getUnsigned(const MIToken &Token, unsigned &Result, - ErrorCallbackType ErrCB) { +static bool getUnsigned(const MIToken &Token, unsigned &Result, + ErrorCallbackType ErrCB) { if (Token.hasIntegerValue()) { const uint64_t Limit = uint64_t(std::numeric_limits<unsigned>::max()) + 1; uint64_t Val64 = Token.integerValue().getLimitedValue(Limit); diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index c732106014e6..7575d1a25e58 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -837,7 +837,7 @@ static bool isTargetDarwin(const MachineFunction &MF) { } // Convenience function to determine whether I is an SVE callee save. -bool IsSVECalleeSave(MachineBasicBlock::iterator I) { +static bool IsSVECalleeSave(MachineBasicBlock::iterator I) { switch (I->getOpcode()) { default: return false; diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index 39e53a75ac7e..9645aa24dc05 100644 --- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -341,9 +341,9 @@ static bool MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode, return true; } -bool MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode, - MachineIRBuilder &MIRBuilder, - const MipsSubtarget &ST) { +static bool MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode, + MachineIRBuilder &MIRBuilder, + const MipsSubtarget &ST) { assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA."); MIRBuilder.buildInstr(Opcode) .add(MI.getOperand(0)) diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index e31023607e80..801c09a317a7 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -1649,7 +1649,7 @@ Instruction *InstCombiner::narrowMathIfNoOverflow(BinaryOperator &BO) { return CastInst::Create(CastOpc, NarrowBO, BO.getType()); } -bool isMergedGEPInBounds(GEPOperator &GEP1, GEPOperator &GEP2) { +static bool isMergedGEPInBounds(GEPOperator &GEP1, GEPOperator &GEP2) { // At least one GEP must be inbounds. if (!GEP1.isInBounds() && !GEP2.isInBounds()) return false; diff --git a/mlir/lib/Analysis/AffineAnalysis.cpp b/mlir/lib/Analysis/AffineAnalysis.cpp index 2608452771fb..5ea87f6bc56a 100644 --- a/mlir/lib/Analysis/AffineAnalysis.cpp +++ b/mlir/lib/Analysis/AffineAnalysis.cpp @@ -117,6 +117,7 @@ static LogicalResult getInstIndexSet(Operation *op, return getIndexSet(loops, indexSet); } +namespace { // ValuePositionMap manages the mapping from Values which represent dimension // and symbol identifiers from 'src' and 'dst' access functions to positions // in new space where some Values are kept separate (using addSrc/DstValue) @@ -195,6 +196,7 @@ class ValuePositionMap { DenseMap<Value, unsigned> dstDimPosMap; DenseMap<Value, unsigned> symbolPosMap; }; +} // namespace // Builds a map from Value to identifier position in a new merged identifier // list, which is the result of merging dim/symbol lists from src/dst @@ -240,12 +242,11 @@ static void buildDimAndSymbolPositionMaps( // Sets up dependence constraints columns appropriately, in the format: // [src-dim-ids, dst-dim-ids, symbol-ids, local-ids, const_term] -void initDependenceConstraints(const FlatAffineConstraints &srcDomain, - const FlatAffineConstraints &dstDomain, - const AffineValueMap &srcAccessMap, - const AffineValueMap &dstAccessMap, - const ValuePositionMap &valuePosMap, - FlatAffineConstraints *dependenceConstraints) { +static void initDependenceConstraints( + const FlatAffineConstraints &srcDomain, + const FlatAffineConstraints &dstDomain, const AffineValueMap &srcAccessMap, + const AffineValueMap &dstAccessMap, const ValuePositionMap &valuePosMap, + FlatAffineConstraints *dependenceConstraints) { // Calculate number of equalities/inequalities and columns required to // initialize FlatAffineConstraints for 'dependenceDomain'. unsigned numIneq = diff --git a/mlir/lib/Analysis/AffineStructures.cpp b/mlir/lib/Analysis/AffineStructures.cpp index b5e314047b05..97f534a727f8 100644 --- a/mlir/lib/Analysis/AffineStructures.cpp +++ b/mlir/lib/Analysis/AffineStructures.cpp @@ -1388,8 +1388,9 @@ static void getLowerAndUpperBoundIndices(const FlatAffineConstraints &cst, // Check if the pos^th identifier can be expressed as a floordiv of an affine // function of other identifiers (where the divisor is a positive constant). // For eg: 4q <= i + j <= 4q + 3 <=> q = (i + j) floordiv 4. -bool detectAsFloorDiv(const FlatAffineConstraints &cst, unsigned pos, - SmallVectorImpl<AffineExpr> *memo, MLIRContext *context) { +static bool detectAsFloorDiv(const FlatAffineConstraints &cst, unsigned pos, + SmallVectorImpl<AffineExpr> *memo, + MLIRContext *context) { assert(pos < cst.getNumIds() && "invalid position"); SmallVector<unsigned, 4> lbIndices, ubIndices; diff --git a/mlir/lib/Analysis/Liveness.cpp b/mlir/lib/Analysis/Liveness.cpp index 26e152dcdf7a..dbda9f5ba289 100644 --- a/mlir/lib/Analysis/Liveness.cpp +++ b/mlir/lib/Analysis/Liveness.cpp @@ -21,6 +21,7 @@ using namespace mlir; +namespace { /// Builds and holds block information during the construction phase. struct BlockInfoBuilder { using ValueSetT = Liveness::ValueSetT; @@ -107,6 +108,7 @@ struct BlockInfoBuilder { /// The set of all used values. ValueSetT useValues; }; +} // namespace /// Builds the internal liveness block mapping. static void buildBlockMapping(MutableArrayRef<Region> regions, diff --git a/mlir/lib/Analysis/Utils.cpp b/mlir/lib/Analysis/Utils.cpp index 4991e51d5f0d..21ca17dce423 100644 --- a/mlir/lib/Analysis/Utils.cpp +++ b/mlir/lib/Analysis/Utils.cpp @@ -471,8 +471,8 @@ static Operation *getInstAtPosition(ArrayRef<unsigned> positions, } // Adds loop IV bounds to 'cst' for loop IVs not found in 'ivs'. -LogicalResult addMissingLoopIVBounds(SmallPtrSet<Value, 8> &ivs, - FlatAffineConstraints *cst) { +static LogicalResult addMissingLoopIVBounds(SmallPtrSet<Value, 8> &ivs, + FlatAffineConstraints *cst) { for (unsigned i = 0, e = cst->getNumDimIds(); i < e; ++i) { auto value = cst->getIdValue(i); if (ivs.count(value) == 0) { diff --git a/mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp b/mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp index 52549933f9d3..a88c9c493c58 100644 --- a/mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp +++ b/mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp @@ -70,6 +70,8 @@ using urem = ValueBuilder<mlir::LLVM::URemOp>; using llvm_alloca = ValueBuilder<LLVM::AllocaOp>; using llvm_return = OperationBuilder<LLVM::ReturnOp>; +namespace { + template <typename T> static LLVMType getPtrToElementType(T containerType, LLVMTypeConverter &lowering) { @@ -104,7 +106,6 @@ static Type convertLinalgType(Type t, LLVMTypeConverter &lowering) { return Type(); } -namespace { /// EDSC-compatible wrapper for MemRefDescriptor. class BaseViewConversionHelper { public: @@ -139,7 +140,6 @@ class BaseViewConversionHelper { MemRefDescriptor d; }; -} // namespace // RangeOp creates a new range descriptor. class RangeOpConversion : public LLVMOpLowering { @@ -421,12 +421,16 @@ static FlatSymbolRefAttr getLibraryCallSymbolRef(Operation *op, return fnNameAttr; } +} // namespace + Type LinalgTypeConverter::convertType(Type t) { if (auto result = LLVMTypeConverter::convertType(t)) return result; return convertLinalgType(t, *this); } +namespace { + // LinalgOpConversion<LinalgOp> creates a new call to the // `LinalgOp::getLibraryCallName()` function. // The implementation of the function can be either in the same module or in an @@ -552,6 +556,8 @@ populateLinalgToStandardConversionPatterns(OwningRewritePatternList &patterns, ctx); } +} // namespace + /// Populate the given list with patterns that convert from Linalg to LLVM. void mlir::populateLinalgToLLVMConversionPatterns( LinalgTypeConverter &converter, OwningRewritePatternList &patterns, diff --git a/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp b/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp index 3ea1f85d62f9..15633ac6d502 100644 --- a/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp +++ b/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp @@ -98,7 +98,7 @@ static Value getOrEmitUpperBound(ForOp forOp, OpBuilder &) { // This roughly corresponds to the "matcher" part of the pattern-based // rewriting infrastructure. template <typename OpTy> -LogicalResult checkLoopNestMappableImpl(OpTy forOp, unsigned numDims) { +static LogicalResult checkLoopNestMappableImpl(OpTy forOp, unsigned numDims) { Region &limit = forOp.region(); for (unsigned i = 0, e = numDims; i < e; ++i) { Operation *nested = &forOp.getBody()->front(); @@ -124,8 +124,8 @@ LogicalResult checkLoopNestMappableImpl(OpTy forOp, unsigned numDims) { } template <typename OpTy> -LogicalResult checkLoopNestMappable(OpTy forOp, unsigned numBlockDims, - unsigned numThreadDims) { +static LogicalResult checkLoopNestMappable(OpTy forOp, unsigned numBlockDims, + unsigned numThreadDims) { if (numBlockDims < 1 || numThreadDims < 1) { LLVM_DEBUG(llvm::dbgs() << "nothing to map"); return success(); @@ -142,8 +142,8 @@ LogicalResult checkLoopNestMappable(OpTy forOp, unsigned numBlockDims, } template <typename OpTy> -LogicalResult checkLoopOpMappable(OpTy forOp, unsigned numBlockDims, - unsigned numThreadDims) { +static LogicalResult checkLoopOpMappable(OpTy forOp, unsigned numBlockDims, + unsigned numThreadDims) { if (numBlockDims < 1 || numThreadDims < 1) { LLVM_DEBUG(llvm::dbgs() << "nothing to map"); return success(); @@ -265,8 +265,8 @@ Optional<OpTy> LoopToGpuConverter::collectBounds(OpTy forOp, /// `nids`. The innermost loop is mapped to the x-dimension, followed by the /// next innermost loop to y-dimension, followed by z-dimension. template <typename OpTy> -OpTy createGPULaunchLoops(OpTy rootForOp, ArrayRef<Value> ids, - ArrayRef<Value> nids) { +static OpTy createGPULaunchLoops(OpTy rootForOp, ArrayRef<Value> ids, + ArrayRef<Value> nids) { auto nDims = ids.size(); assert(nDims == nids.size()); for (auto dim : llvm::seq<unsigned>(0, nDims)) { @@ -285,9 +285,10 @@ OpTy createGPULaunchLoops(OpTy rootForOp, ArrayRef<Value> ids, /// Utility method to convert the gpu::KernelDim3 object for representing id of /// each workgroup/workitem and number of workgroup/workitems along a dimension /// of the launch into a container. -void packIdAndNumId(gpu::KernelDim3 kernelIds, gpu::KernelDim3 kernelNids, - unsigned nDims, SmallVectorImpl<Value> &ids, - SmallVectorImpl<Value> &nids) { +static void packIdAndNumId(gpu::KernelDim3 kernelIds, + gpu::KernelDim3 kernelNids, unsigned nDims, + SmallVectorImpl<Value> &ids, + SmallVectorImpl<Value> &nids) { assert(nDims <= 3 && "invalid number of launch dimensions"); SmallVector<Value, 3> allIds = {kernelIds.z, kernelIds.y, kernelIds.x}; SmallVector<Value, 3> allNids = {kernelNids.z, kernelNids.y, kernelNids.x}; @@ -300,9 +301,9 @@ void packIdAndNumId(gpu::KernelDim3 kernelIds, gpu::KernelDim3 kernelNids, /// Generate the body of the launch operation. template <typename OpTy> -LogicalResult createLaunchBody(OpBuilder &builder, OpTy rootForOp, - gpu::LaunchOp launchOp, unsigned numBlockDims, - unsigned numThreadDims) { +static LogicalResult +createLaunchBody(OpBuilder &builder, OpTy rootForOp, gpu::LaunchOp launchOp, + unsigned numBlockDims, unsigned numThreadDims) { OpBuilder::InsertionGuard bodyInsertionGuard(builder); builder.setInsertionPointToEnd(&launchOp.body().front()); auto returnOp = builder.create<gpu::ReturnOp>(launchOp.getLoc()); @@ -337,8 +338,9 @@ LogicalResult createLaunchBody(OpBuilder &builder, OpTy rootForOp, // Convert the computation rooted at the `rootForOp`, into a GPU kernel with the // given workgroup size and number of workgroups. template <typename OpTy> -LogicalResult createLaunchFromOp(OpTy rootForOp, ArrayRef<Value> numWorkGroups, - ArrayRef<Value> workGroupSizes) { +static LogicalResult createLaunchFromOp(OpTy rootForOp, + ArrayRef<Value> numWorkGroups, + ArrayRef<Value> workGroupSizes) { OpBuilder builder(rootForOp.getOperation()); if (numWorkGroups.size() > 3) { return rootForOp.emitError("invalid ") diff --git a/mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp b/mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp index 7e7b7ef6ea66..cc535b938fb8 100644 --- a/mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp +++ b/mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp @@ -139,10 +139,11 @@ class StoreOpConversion final : public SPIRVOpLowering<StoreOp> { // TODO(ravishankarm) : This method assumes that the `origBaseType` is a // MemRefType with AffineMap that has static strides. Handle dynamic strides -spirv::AccessChainOp getElementPtr(OpBuilder &builder, - SPIRVTypeConverter &typeConverter, - Location loc, MemRefType origBaseType, - Value basePtr, ArrayRef<Value> indices) { +static spirv::AccessChainOp getElementPtr(OpBuilder &builder, + SPIRVTypeConverter &typeConverter, + Location loc, MemRefType origBaseType, + Value basePtr, + ArrayRef<Value> indices) { // Get base and offset of the MemRefType and verify they are static. int64_t offset; SmallVector<int64_t, 4> strides; diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp index cc6636df00ee..8ec3212f7c0c 100644 --- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp +++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp @@ -34,6 +34,8 @@ using namespace mlir; using namespace mlir::vector; +namespace { + template <typename T> static LLVM::LLVMType getPtrToElementType(T containerType, LLVMTypeConverter &lowering) { @@ -948,6 +950,8 @@ class VectorStridedSliceOpConversion : public OpRewritePattern<StridedSliceOp> { } }; +} // namespace + /// Populate the given list with patterns that convert from Vector to LLVM. void mlir::populateVectorToLLVMConversionPatterns( LLVMTypeConverter &converter, OwningRewritePatternList &patterns) { diff --git a/mlir/lib/Dialect/AffineOps/AffineOps.cpp b/mlir/lib/Dialect/AffineOps/AffineOps.cpp index 0da539ea9f08..f846adaf4c42 100644 --- a/mlir/lib/Dialect/AffineOps/AffineOps.cpp +++ b/mlir/lib/Dialect/AffineOps/AffineOps.cpp @@ -141,7 +141,8 @@ bool mlir::isValidDim(Value value) { /// Returns true if the 'index' dimension of the `memref` defined by /// `memrefDefOp` is a statically shaped one or defined using a valid symbol. template <typename AnyMemRefDefOp> -bool isMemRefSizeValidSymbol(AnyMemRefDefOp memrefDefOp, unsigned index) { +static bool isMemRefSizeValidSymbol(AnyMemRefDefOp memrefDefOp, + unsigned index) { auto memRefType = memrefDefOp.getType(); // Statically shaped. if (!ShapedType::isDynamic(memRefType.getDimSize(index))) @@ -1620,7 +1621,8 @@ static LogicalResult verify(AffineIfOp op) { return success(); } -ParseResult parseAffineIfOp(OpAsmParser &parser, OperationState &result) { +static ParseResult parseAffineIfOp(OpAsmParser &parser, + OperationState &result) { // Parse the condition attribute set. IntegerSetAttr conditionAttr; unsigned numDims; @@ -1667,7 +1669,7 @@ ParseResult parseAffineIfOp(OpAsmParser &parser, OperationState &result) { return success(); } -void print(OpAsmPrinter &p, AffineIfOp op) { +static void print(OpAsmPrinter &p, AffineIfOp op) { auto conditionAttr = op.getAttrOfType<IntegerSetAttr>(op.getConditionAttrName()); p << "affine.if " << conditionAttr; @@ -2057,7 +2059,7 @@ static ParseResult parseAffinePrefetchOp(OpAsmParser &parser, return success(); } -void print(OpAsmPrinter &p, AffinePrefetchOp op) { +static void print(OpAsmPrinter &p, AffinePrefetchOp op) { p << AffinePrefetchOp::getOperationName() << " " << op.memref() << '['; AffineMapAttr mapAttr = op.getAttrOfType<AffineMapAttr>(op.getMapAttrName()); if (mapAttr) { @@ -2074,7 +2076,7 @@ void print(OpAsmPrinter &p, AffinePrefetchOp op) { p << " : " << op.getMemRefType(); } -LogicalResult verify(AffinePrefetchOp op) { +static LogicalResult verify(AffinePrefetchOp op) { auto mapAttr = op.getAttrOfType<AffineMapAttr>(op.getMapAttrName()); if (mapAttr) { AffineMap map = mapAttr.getValue(); diff --git a/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp b/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp index dbca1fb003a5..083e28260201 100644 --- a/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp +++ b/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp @@ -258,7 +258,7 @@ iterator_range<Block::args_iterator> LaunchOp::getKernelArguments() { return llvm::drop_begin(args, LaunchOp::kNumConfigRegionAttributes); } -LogicalResult verify(LaunchOp op) { +static LogicalResult verify(LaunchOp op) { // Kernel launch takes kNumConfigOperands leading operands for grid/block // sizes and transforms them into kNumConfigRegionAttributes region arguments // for block/thread identifiers and grid/block sizes. @@ -300,7 +300,7 @@ static void printSizeAssignment(OpAsmPrinter &p, KernelDim3 size, p << size.z << " = " << operands[2] << ')'; } -void printLaunchOp(OpAsmPrinter &p, LaunchOp op) { +static void printLaunchOp(OpAsmPrinter &p, LaunchOp op) { ValueRange operands = op.getOperands(); // Print the launch configuration. @@ -370,7 +370,7 @@ parseSizeAssignment(OpAsmParser &parser, // (`args` ssa-reassignment `:` type-list)? // region attr-dict? // ssa-reassignment ::= `(` ssa-id `=` ssa-use (`,` ssa-id `=` ssa-use)* `)` -ParseResult parseLaunchOp(OpAsmParser &parser, OperationState &result) { +static ParseResult parseLaunchOp(OpAsmParser &parser, OperationState &result) { // Sizes of the grid and block. SmallVector<OpAsmParser::OperandType, LaunchOp::kNumConfigOperands> sizes( LaunchOp::kNumConfigOperands); @@ -549,7 +549,7 @@ KernelDim3 LaunchFuncOp::getBlockSizeOperandValues() { return KernelDim3{getOperand(3), getOperand(4), getOperand(5)}; } -LogicalResult verify(LaunchFuncOp op) { +static LogicalResult verify(LaunchFuncOp op) { auto module = op.getParentOfType<ModuleOp>(); if (!module) return op.emitOpError("expected to belong to a module"); @@ -729,7 +729,7 @@ static void printAttributions(OpAsmPrinter &p, StringRef keyword, } /// Prints a GPU Func op. -void printGPUFuncOp(OpAsmPrinter &p, GPUFuncOp op) { +static void printGPUFuncOp(OpAsmPrinter &p, GPUFuncOp op) { p << GPUFuncOp::getOperationName() << ' '; p.printSymbolName(op.getName()); diff --git a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp index a8be9b20b447..384d24957f46 100644 --- a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp +++ b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp @@ -109,7 +109,7 @@ static ParseResult parseGenericOp(OpAsmParser &parser, OperationState &result) { } template <typename GenericOpType> -LogicalResult verifyBlockArgs(GenericOpType op, Block &block); +static LogicalResult verifyBlockArgs(GenericOpType op, Block &block); template <> LogicalResult verifyBlockArgs(GenericOp op, Block &block) { auto nViews = op.getNumInputsAndOutputs(); @@ -158,7 +158,7 @@ template <> LogicalResult verifyBlockArgs(IndexedGenericOp op, Block &block) { } template <typename GenericOpType> -LogicalResult verifyFuncArgs(GenericOpType op, FunctionType funType); +static LogicalResult verifyFuncArgs(GenericOpType op, FunctionType funType); template <> LogicalResult verifyFuncArgs(GenericOp op, FunctionType funType) { auto nViews = op.getNumInputsAndOutputs(); @@ -228,7 +228,7 @@ LogicalResult verifyFuncArgs(IndexedGenericOp op, FunctionType funType) { } template <typename GenericOpType> -LogicalResult verifyGenericOp(GenericOpType op) { +static LogicalResult verifyGenericOp(GenericOpType op) { auto nInputViews = op.getNumInputs(); auto nLoops = op.getNumLoops(); auto nViews = op.getNumInputsAndOutputs(); @@ -729,7 +729,7 @@ static ParseResult parseYieldOp(OpAsmParser &parser, OperationState &result) { } template <typename GenericOpType> -LogicalResult verifyYield(YieldOp op, GenericOpType genericOp) { +static LogicalResult verifyYield(YieldOp op, GenericOpType genericOp) { // The operand number and types must match the view element types. auto nOutputViews = genericOp.getNumOutputs(); if (op.getNumOperands() != nOutputViews) diff --git a/mlir/lib/Dialect/Linalg/Transforms/LinalgToLoops.cpp b/mlir/lib/Dialect/Linalg/Transforms/LinalgToLoops.cpp index c9f4b34ebc0e..f5dac8aced15 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/LinalgToLoops.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/LinalgToLoops.cpp @@ -37,6 +37,8 @@ using IndexedAffineValue = TemplatedIndexedValue<affine_load, affine_store>; using edsc::op::operator+; using edsc::op::operator==; +namespace { + static SmallVector<ValueHandle, 8> makeCanonicalAffineApplies(OpBuilder &b, Location loc, AffineMap map, ArrayRef<Value> vals) { @@ -379,7 +381,6 @@ class LinalgScopedEmitter<IndexedValueType, IndexedGenericOp> { } }; -namespace { // This struct is for factoring out the implementation and support template // instantiations in the following 2 cases: // 1. Appending to a list of patterns via RewritePatternList. @@ -393,7 +394,6 @@ class LinalgOpToLoopsImpl { public: static LogicalResult doit(Operation *op, PatternRewriter &rewriter); }; -} // namespace template <typename LoopTy, typename IndexedValueTy, typename ConcreteOpTy> LogicalResult LinalgOpToLoopsImpl<LoopTy, IndexedValueTy, ConcreteOpTy>::doit( @@ -538,6 +538,8 @@ void LowerLinalgToLoopsPass<LoopType, IndexedValueType>::runOnFunction() { applyPatternsGreedily(this->getFunction(), patterns); } +} // namespace + /// Create a pass to convert Linalg operations to loop.for loops and /// std.load/std.store accesses. std::unique_ptr<OpPassBase<FuncOp>> diff --git a/mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp b/mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp index b77f658aa2fe..bcf6576abbb3 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp @@ -170,7 +170,7 @@ struct TileCheck : public AffineExprVisitor<TileCheck> { // // TODO(pifon, ntv): Investigate whether mixing implicit and explicit indices // does not lead to losing information. -void transformIndexedGenericOpIndices( +static void transformIndexedGenericOpIndices( OpBuilder &b, LinalgOp op, ArrayRef<ValueHandle *> pivs, const LoopIndexToRangeIndexMap &loopIndexToRangeIndex) { auto indexedGenericOp = dyn_cast<IndexedGenericOp>(op.getOperation()); diff --git a/mlir/lib/Dialect/LoopOps/LoopOps.cpp b/mlir/lib/Dialect/LoopOps/LoopOps.cpp index 7e3e286b842f..8effe71088c1 100644 --- a/mlir/lib/Dialect/LoopOps/LoopOps.cpp +++ b/mlir/lib/Dialect/LoopOps/LoopOps.cpp @@ -68,7 +68,7 @@ void ForOp::build(Builder *builder, OperationState &result, Value lb, Value ub, bodyRegion->front().addArgument(builder->getIndexType()); } -LogicalResult verify(ForOp op) { +static LogicalResult verify(ForOp op) { if (auto cst = dyn_cast_or_null<ConstantIndexOp>(op.step().getDefiningOp())) if (cst.getValue() <= 0) return op.emitOpError("constant step operand must be positive"); diff --git a/mlir/lib/Dialect/QuantOps/Transforms/ConvertSimQuant.cpp b/mlir/lib/Dialect/QuantOps/Transforms/ConvertSimQuant.cpp index 2a4c14f2231f..ffd7efb21bdb 100644 --- a/mlir/lib/Dialect/QuantOps/Transforms/ConvertSimQuant.cpp +++ b/mlir/lib/Dialect/QuantOps/Transforms/ConvertSimQuant.cpp @@ -26,8 +26,6 @@ class ConvertSimulatedQuantPass void runOnFunction() override; }; -} // end anonymous namespace - /// Base class rewrites ConstFakeQuant into a qbarrier/dbarrier pair. template <typename ConcreteRewriteClass, typename FakeQuantOp> class FakeQuantRewrite : public OpRewritePattern<FakeQuantOp> { @@ -126,6 +124,8 @@ class ConstFakeQuantPerAxisRewrite } }; +} // namespace + void ConvertSimulatedQuantPass::runOnFunction() { bool hadFailure = false; OwningRewritePatternList patterns; diff --git a/mlir/lib/Dialect/SDBM/SDBMExpr.cpp b/mlir/lib/Dialect/SDBM/SDBMExpr.cpp index 68e3e1c278ec..ae2f447796e4 100644 --- a/mlir/lib/Dialect/SDBM/SDBMExpr.cpp +++ b/mlir/lib/Dialect/SDBM/SDBMExpr.cpp @@ -301,8 +301,9 @@ AffineExpr SDBMExpr::getAsAffineExpr() const { // expression is already a sum expression, update its constant and extract the // LHS if the constant becomes zero. Otherwise, construct a sum expression. template <typename Result> -Result addConstantAndSink(SDBMDirectExpr expr, int64_t constant, bool negated, - function_ref<Result(SDBMDirectExpr)> builder) { +static Result addConstantAndSink(SDBMDirectExpr expr, int64_t constant, + bool negated, + function_ref<Result(SDBMDirectExpr)> builder) { SDBMDialect *dialect = expr.getDialect(); if (auto sumExpr = expr.dyn_cast<SDBMSumExpr>()) { if (negated) diff --git a/mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp b/mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp index 98c36fb9b081..0e543df29b64 100644 --- a/mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp +++ b/mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp @@ -375,6 +375,7 @@ Optional<uint64_t> parseAndVerify<uint64_t>(SPIRVDialect const &dialect, return parseAndVerifyInteger<uint64_t>(dialect, parser); } +namespace { // Functor object to parse a comma separated list of specs. The function // parseAndVerify does the actual parsing and verification of individual // elements. This is a functor since parsing the last element of the list @@ -407,6 +408,7 @@ template <typename ParseType> struct parseCommaSeparatedList<ParseType> { return llvm::None; } }; +} // namespace // dim ::= `1D` | `2D` | `3D` | `Cube` | <and other SPIR-V Dim specifiers...> // diff --git a/mlir/lib/Dialect/SPIRV/Serialization/TranslateRegistration.cpp b/mlir/lib/Dialect/SPIRV/Serialization/TranslateRegistration.cpp index 750710fa3d99..46596741ea07 100644 --- a/mlir/lib/Dialect/SPIRV/Serialization/TranslateRegistration.cpp +++ b/mlir/lib/Dialect/SPIRV/Serialization/TranslateRegistration.cpp @@ -33,8 +33,8 @@ using namespace mlir; // Deserializes the SPIR-V binary module stored in the file named as // `inputFilename` and returns a module containing the SPIR-V module. -OwningModuleRef deserializeModule(const llvm::MemoryBuffer *input, - MLIRContext *context) { +static OwningModuleRef deserializeModule(const llvm::MemoryBuffer *input, + MLIRContext *context) { Builder builder(context); // Make sure the input stream can be treated as a stream of SPIR-V words @@ -71,7 +71,7 @@ static TranslateToMLIRRegistration fromBinary( // Serialization registration //===----------------------------------------------------------------------===// -LogicalResult serializeModule(ModuleOp module, raw_ostream &output) { +static LogicalResult serializeModule(ModuleOp module, raw_ostream &output) { if (!module) return failure(); @@ -104,8 +104,9 @@ static TranslateFromMLIRRegistration // Round-trip registration //===----------------------------------------------------------------------===// -LogicalResult roundTripModule(llvm::SourceMgr &sourceMgr, raw_ostream &output, - MLIRContext *context) { +static LogicalResult roundTripModule(llvm::SourceMgr &sourceMgr, + raw_ostream &output, + MLIRContext *context) { // Parse an MLIR module from the source manager. auto srcModule = OwningModuleRef(parseSourceFile(sourceMgr, context)); if (!srcModule) diff --git a/mlir/lib/Dialect/VectorOps/VectorOps.cpp b/mlir/lib/Dialect/VectorOps/VectorOps.cpp index f2742de8428f..b26f70adbba5 100644 --- a/mlir/lib/Dialect/VectorOps/VectorOps.cpp +++ b/mlir/lib/Dialect/VectorOps/VectorOps.cpp @@ -918,9 +918,10 @@ static ParseResult parseInsertStridedSliceOp(OpAsmParser &parser, // TODO(ntv) Should be moved to Tablegen Confined attributes. template <typename OpType> -LogicalResult isIntegerArrayAttrSmallerThanShape(OpType op, ArrayAttr arrayAttr, - ArrayRef<int64_t> shape, - StringRef attrName) { +static LogicalResult isIntegerArrayAttrSmallerThanShape(OpType op, + ArrayAttr arrayAttr, + ArrayRef<int64_t> shape, + StringRef attrName) { if (arrayAttr.size() > shape.size()) return op.emitOpError("expected ") << attrName << " attribute of rank smaller than vector rank"; @@ -931,10 +932,10 @@ LogicalResult isIntegerArrayAttrSmallerThanShape(OpType op, ArrayAttr arrayAttr, // interval. If `halfOpen` is true then the admissible interval is [min, max). // Otherwise, the admissible interval is [min, max]. template <typename OpType> -LogicalResult isIntegerArrayAttrConfinedToRange(OpType op, ArrayAttr arrayAttr, - int64_t min, int64_t max, - StringRef attrName, - bool halfOpen = true) { +static LogicalResult +isIntegerArrayAttrConfinedToRange(OpType op, ArrayAttr arrayAttr, int64_t min, + int64_t max, StringRef attrName, + bool halfOpen = true) { for (auto attr : arrayAttr) { auto val = attr.cast<IntegerAttr>().getInt(); auto upper = max; @@ -951,7 +952,7 @@ LogicalResult isIntegerArrayAttrConfinedToRange(OpType op, ArrayAttr arrayAttr, // interval. If `halfOpen` is true then the admissible interval is [min, max). // Otherwise, the admissible interval is [min, max]. template <typename OpType> -LogicalResult +static LogicalResult isIntegerArrayAttrConfinedToShape(OpType op, ArrayAttr arrayAttr, ArrayRef<int64_t> shape, StringRef attrName, bool halfOpen = true, int64_t min = 0) { @@ -975,7 +976,7 @@ isIntegerArrayAttrConfinedToShape(OpType op, ArrayAttr arrayAttr, // interval. If `halfOpen` is true then the admissible interval is [min, max). // Otherwise, the admissible interval is [min, max]. template <typename OpType> -LogicalResult isSumOfIntegerArrayAttrConfinedToShape( +static LogicalResult isSumOfIntegerArrayAttrConfinedToShape( OpType op, ArrayAttr arrayAttr1, ArrayAttr arrayAttr2, ArrayRef<int64_t> shape, StringRef attrName1, StringRef attrName2, bool halfOpen = true, int64_t min = 1) { @@ -1470,7 +1471,8 @@ static void print(OpAsmPrinter &p, TransferReadOp op) { p << " : " << op.getMemRefType() << ", " << op.getVectorType(); } -ParseResult parseTransferReadOp(OpAsmParser &parser, OperationState &result) { +static ParseResult parseTransferReadOp(OpAsmParser &parser, + OperationState &result) { llvm::SMLoc typesLoc; OpAsmParser::OperandType memrefInfo; SmallVector<OpAsmParser::OperandType, 8> indexInfo; @@ -1545,7 +1547,8 @@ static void print(OpAsmPrinter &p, TransferWriteOp op) { p << " : " << op.getVectorType() << ", " << op.getMemRefType(); } -ParseResult parseTransferWriteOp(OpAsmParser &parser, OperationState &result) { +static ParseResult parseTransferWriteOp(OpAsmParser &parser, + OperationState &result) { llvm::SMLoc typesLoc; OpAsmParser::OperandType storeValueInfo; OpAsmParser::OperandType memRefInfo; @@ -1682,7 +1685,8 @@ static LogicalResult verify(TupleGetOp op) { // ConstantMaskOp //===----------------------------------------------------------------------===// -ParseResult parseConstantMaskOp(OpAsmParser &parser, OperationState &result) { +static ParseResult parseConstantMaskOp(OpAsmParser &parser, + OperationState &result) { Type resultType; ArrayAttr maskDimSizesAttr; StringRef attrName = ConstantMaskOp::getMaskDimSizesAttrName(); @@ -1729,7 +1733,8 @@ static LogicalResult verify(ConstantMaskOp &op) { // CreateMaskOp //===----------------------------------------------------------------------===// -ParseResult parseCreateMaskOp(OpAsmParser &parser, OperationState &result) { +static ParseResult parseCreateMaskOp(OpAsmParser &parser, + OperationState &result) { auto indexType = parser.getBuilder().getIndexType(); Type resultType; SmallVector<OpAsmParser::OperandType, 4> operandInfo; @@ -1758,7 +1763,7 @@ static LogicalResult verify(CreateMaskOp op) { // PrintOp //===----------------------------------------------------------------------===// -ParseResult parsePrintOp(OpAsmParser &parser, OperationState &result) { +static ParseResult parsePrintOp(OpAsmParser &parser, OperationState &result) { OpAsmParser::OperandType source; Type sourceType; return failure(parser.parseOperand(source) || diff --git a/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp b/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp index d98f41e3d63e..c86c4325d794 100644 --- a/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp +++ b/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp @@ -522,6 +522,7 @@ generateTransferOpSlices(VectorType vectorType, TupleType tupleType, } } +namespace { // Splits vector TransferReadOp into smaller TransferReadOps based on slicing // scheme of its unique ExtractSlicesOp user. struct SplitTransferReadOp : public OpRewritePattern<vector::TransferReadOp> { @@ -657,6 +658,8 @@ struct TupleGetFolderOp : public OpRewritePattern<vector::TupleGetOp> { } }; +} // namespace + // TODO(andydavis) Add pattern to rewrite ExtractSlices(ConstantMaskOp). // TODO(andydavis) Add this as DRR pattern. void mlir::vector::populateVectorToVectorTransformationPatterns( diff --git a/mlir/lib/ExecutionEngine/ExecutionEngine.cpp b/mlir/lib/ExecutionEngine/ExecutionEngine.cpp index 1537018076ab..651c90a87d71 100644 --- a/mlir/lib/ExecutionEngine/ExecutionEngine.cpp +++ b/mlir/lib/ExecutionEngine/ExecutionEngine.cpp @@ -122,7 +122,7 @@ static std::string makePackedFunctionName(StringRef name) { // For each function in the LLVM module, define an interface function that wraps // all the arguments of the original function and all its results into an i8** // pointer to provide a unified invocation interface. -void packFunctionArguments(Module *module) { +static void packFunctionArguments(Module *module) { auto &ctx = module->getContext(); llvm::IRBuilder<> builder(ctx); DenseSet<llvm::Function *> interfaceFunctions; diff --git a/mlir/lib/IR/SymbolTable.cpp b/mlir/lib/IR/SymbolTable.cpp index ed9de48c400b..ee4bc9ad57a4 100644 --- a/mlir/lib/IR/SymbolTable.cpp +++ b/mlir/lib/IR/SymbolTable.cpp @@ -674,8 +674,8 @@ static Attribute rebuildAttrAfterRAUW( } /// Generates a new symbol reference attribute with a new leaf reference. -SymbolRefAttr generateNewRefAttr(SymbolRefAttr oldAttr, - FlatSymbolRefAttr newLeafAttr) { +static SymbolRefAttr generateNewRefAttr(SymbolRefAttr oldAttr, + FlatSymbolRefAttr newLeafAttr) { if (oldAttr.isa<FlatSymbolRefAttr>()) return newLeafAttr; auto nestedRefs = llvm::to_vector<2>(oldAttr.getNestedReferences()); diff --git a/mlir/lib/Pass/PassStatistics.cpp b/mlir/lib/Pass/PassStatistics.cpp index 0ab656c20547..7ad11f012f75 100644 --- a/mlir/lib/Pass/PassStatistics.cpp +++ b/mlir/lib/Pass/PassStatistics.cpp @@ -135,7 +135,7 @@ static void printResultsAsPipeline(raw_ostream &os, OpPassManager &pm) { printPass(/*indent=*/0, &pass); } -void printStatistics(OpPassManager &pm, PassDisplayMode displayMode) { +static void printStatistics(OpPassManager &pm, PassDisplayMode displayMode) { auto os = llvm::CreateInfoOutputFile(); // Print the stats header. diff --git a/mlir/lib/Transforms/Utils/LoopUtils.cpp b/mlir/lib/Transforms/Utils/LoopUtils.cpp index 9d7e7cddb05e..441d95fa698c 100644 --- a/mlir/lib/Transforms/Utils/LoopUtils.cpp +++ b/mlir/lib/Transforms/Utils/LoopUtils.cpp @@ -351,7 +351,7 @@ LogicalResult mlir::instBodySkew(AffineForOp forOp, ArrayRef<uint64_t> shifts, // in the parent loop. Collect at most `maxLoops` loops and append them to // `forOps`. template <typename T> -void getPerfectlyNestedLoopsImpl( +static void getPerfectlyNestedLoopsImpl( SmallVectorImpl<T> &forOps, T rootForOp, unsigned maxLoops = std::numeric_limits<unsigned>::max()) { for (unsigned i = 0; i < maxLoops; ++i) { diff --git a/mlir/test/lib/TestDialect/TestPatterns.cpp b/mlir/test/lib/TestDialect/TestPatterns.cpp index 62ee89e0fe4c..bbeb2c627617 100644 --- a/mlir/test/lib/TestDialect/TestPatterns.cpp +++ b/mlir/test/lib/TestDialect/TestPatterns.cpp @@ -21,7 +21,8 @@ static void createOpI(PatternRewriter &rewriter, Value input) { rewriter.create<OpI>(rewriter.getUnknownLoc(), input); } -void handleNoResultOp(PatternRewriter &rewriter, OpSymbolBindingNoResult op) { +static void handleNoResultOp(PatternRewriter &rewriter, + OpSymbolBindingNoResult op) { // Turn the no result op to a one-result op. rewriter.create<OpSymbolBindingB>(op.getLoc(), op.operand().getType(), op.operand()); @@ -56,6 +57,7 @@ static mlir::PassRegistration<TestPatternDriver> // ReturnType Driver. //===----------------------------------------------------------------------===// +namespace { struct ReturnTypeOpMatch : public RewritePattern { ReturnTypeOpMatch(MLIRContext *ctx) : RewritePattern(OpWithInferTypeInterfaceOp::getOperationName(), 1, ctx) { @@ -94,7 +96,6 @@ struct ReturnTypeOpMatch : public RewritePattern { } }; -namespace { struct TestReturnTypeDriver : public FunctionPass<TestReturnTypeDriver> { void runOnFunction() override { mlir::OwningRewritePatternList patterns; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
