dmgreen added a comment.
Looks good to me, with a couple of minor nitpicks (that I'm not sure matter or
not).
================
Comment at: llvm/lib/Target/ARM/ARMInstrMVE.td:3626
-class MVE_VxMULH<string iname, string suffix, bit U, bits<2> size,
+class MVE_VxMULH<string iname, string suffix, bits<2> size, bit U,
bit round, list<dag> pattern=[]>
----------------
Any strong reason to switch these around? From what I can tell most of the
patterns are (suffix, unsigned, size) in that order. Although that doesn't seem
to be universal. Might as well try to keep it consistent, if you do not have a
reason to swap them.
================
Comment at: llvm/lib/Target/ARM/ARMInstrMVE.td:3644
+multiclass MVE_VxMULH_m<string iname, MVEVectorVTInfo VTI,
+ SDNode unpred_op, Intrinsic pred_int,
+ bit round> {
----------------
Formatting.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D70948/new/
https://reviews.llvm.org/D70948
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
