mhorne created this revision.
mhorne added reviewers: asb, apazos, shiva0217.
Herald added subscribers: cfe-commits, jocewei, PkmX, rkruppe, the_o,
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, kito-cheng,
niosHD, sabuasal, simoncook, johnrusso, rbar.
Herald added a project: clang.
GCC supports a small number of RISC-V specific inline assembly
constraints, while currently clang only supports the machine independent
ones for RISC-V targets. Add parsing for these constraints, based on
their descriptions in the GCC documentation [1].
[1]
https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html#Machine-Constraints
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D61098
Files:
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/Basic/Targets/RISCV.h
Index: clang/lib/Basic/Targets/RISCV.h
===================================================================
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -61,9 +61,7 @@
ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &Info) const override {
- return false;
- }
+ TargetInfo::ConstraintInfo &Info) const override;
bool hasFeature(StringRef Feature) const override;
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -39,6 +39,27 @@
return llvm::makeArrayRef(GCCRegAliases);
}
+bool RISCVTargetInfo::validateAsmConstraint(
+ const char *&Name, TargetInfo::ConstraintInfo &Info) const {
+ switch (*Name) {
+ default:
+ return false;
+ case 'f': // floating-point register.
+ case 'A': // address held in a general purpose register.
+ Info.setAllowsRegister();
+ return true;
+ case 'I': // I-type 12-bit signed immediate.
+ Info.setRequiresImmediate(-2048, 2047);
+ return true;
+ case 'J': // integer zero.
+ Info.setRequiresImmediate(0);
+ return true;
+ case 'K': // 5-bit unsigned immediate for accessing CSRs.
+ Info.setRequiresImmediate(0, 31);
+ return true;
+ }
+}
+
void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ELF__");
Index: clang/lib/Basic/Targets/RISCV.h
===================================================================
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -61,9 +61,7 @@
ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &Info) const override {
- return false;
- }
+ TargetInfo::ConstraintInfo &Info) const override;
bool hasFeature(StringRef Feature) const override;
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -39,6 +39,27 @@
return llvm::makeArrayRef(GCCRegAliases);
}
+bool RISCVTargetInfo::validateAsmConstraint(
+ const char *&Name, TargetInfo::ConstraintInfo &Info) const {
+ switch (*Name) {
+ default:
+ return false;
+ case 'f': // floating-point register.
+ case 'A': // address held in a general purpose register.
+ Info.setAllowsRegister();
+ return true;
+ case 'I': // I-type 12-bit signed immediate.
+ Info.setRequiresImmediate(-2048, 2047);
+ return true;
+ case 'J': // integer zero.
+ Info.setRequiresImmediate(0);
+ return true;
+ case 'K': // 5-bit unsigned immediate for accessing CSRs.
+ Info.setRequiresImmediate(0, 31);
+ return true;
+ }
+}
+
void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ELF__");
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