Merged to 8.0 in r352860.
On Tue, Jan 29, 2019 at 10:03 AM Sam Parker via cfe-commits <cfe-commits@lists.llvm.org> wrote: > > Author: sam_parker > Date: Tue Jan 29 01:04:03 2019 > New Revision: 352463 > > URL: http://llvm.org/viewvc/llvm-project?rev=352463&view=rev > Log: > [AArch64] Update int64_t ACLE builtin arguments > > Re-applying r351740 with fixes (changing LL to W). > > Differential Revision: https://reviews.llvm.org/D56852 > > Modified: > cfe/trunk/include/clang/Basic/BuiltinsAArch64.def > cfe/trunk/test/CodeGen/arm64-crc32.c > cfe/trunk/test/CodeGen/builtins-arm64.c > > Modified: cfe/trunk/include/clang/Basic/BuiltinsAArch64.def > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsAArch64.def?rev=352463&r1=352462&r2=352463&view=diff > ============================================================================== > --- cfe/trunk/include/clang/Basic/BuiltinsAArch64.def (original) > +++ cfe/trunk/include/clang/Basic/BuiltinsAArch64.def Tue Jan 29 01:04:03 2019 > @@ -32,7 +32,7 @@ BUILTIN(__builtin_arm_clrex, "v", "") > > // Bit manipulation > BUILTIN(__builtin_arm_rbit, "UiUi", "nc") > -BUILTIN(__builtin_arm_rbit64, "LUiLUi", "nc") > +BUILTIN(__builtin_arm_rbit64, "WUiWUi", "nc") > > // HINT > BUILTIN(__builtin_arm_nop, "v", "") > @@ -49,8 +49,8 @@ BUILTIN(__builtin_arm_crc32h, "UiUiUs", > BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc") > BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc") > BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc") > -BUILTIN(__builtin_arm_crc32d, "UiUiLUi", "nc") > -BUILTIN(__builtin_arm_crc32cd, "UiUiLUi", "nc") > +BUILTIN(__builtin_arm_crc32d, "UiUiWUi", "nc") > +BUILTIN(__builtin_arm_crc32cd, "UiUiWUi", "nc") > > // Memory barrier > BUILTIN(__builtin_arm_dmb, "vUi", "nc") > @@ -62,10 +62,10 @@ BUILTIN(__builtin_arm_prefetch, "vvC*UiU > > // System Registers > BUILTIN(__builtin_arm_rsr, "UicC*", "nc") > -BUILTIN(__builtin_arm_rsr64, "LUicC*", "nc") > +BUILTIN(__builtin_arm_rsr64, "WUicC*", "nc") > BUILTIN(__builtin_arm_rsrp, "v*cC*", "nc") > BUILTIN(__builtin_arm_wsr, "vcC*Ui", "nc") > -BUILTIN(__builtin_arm_wsr64, "vcC*LUi", "nc") > +BUILTIN(__builtin_arm_wsr64, "vcC*WUi", "nc") > BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc") > > // MSVC > > Modified: cfe/trunk/test/CodeGen/arm64-crc32.c > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm64-crc32.c?rev=352463&r1=352462&r2=352463&view=diff > ============================================================================== > --- cfe/trunk/test/CodeGen/arm64-crc32.c (original) > +++ cfe/trunk/test/CodeGen/arm64-crc32.c Tue Jan 29 01:04:03 2019 > @@ -1,54 +1,57 @@ > // REQUIRES: aarch64-registered-target > // RUN: %clang_cc1 -triple arm64-none-linux-gnu \ > // RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | > FileCheck %s > +// RUN: %clang_cc1 -triple aarch64-windows \ > +// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | > FileCheck %s > +#include <stdint.h> > > -int crc32b(int a, char b) > +uint32_t crc32b(uint32_t a, uint8_t b) > { > return __builtin_arm_crc32b(a,b); > // CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32 > // CHECK: call i32 @llvm.aarch64.crc32b(i32 %a, i32 [[T0]]) > } > > -int crc32cb(int a, char b) > +uint32_t crc32cb(uint32_t a, uint8_t b) > { > return __builtin_arm_crc32cb(a,b); > // CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32 > // CHECK: call i32 @llvm.aarch64.crc32cb(i32 %a, i32 [[T0]]) > } > > -int crc32h(int a, short b) > +uint32_t crc32h(uint32_t a, uint16_t b) > { > return __builtin_arm_crc32h(a,b); > // CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32 > // CHECK: call i32 @llvm.aarch64.crc32h(i32 %a, i32 [[T0]]) > } > > -int crc32ch(int a, short b) > +uint32_t crc32ch(uint32_t a, uint16_t b) > { > return __builtin_arm_crc32ch(a,b); > // CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32 > // CHECK: call i32 @llvm.aarch64.crc32ch(i32 %a, i32 [[T0]]) > } > > -int crc32w(int a, int b) > +uint32_t crc32w(uint32_t a, uint32_t b) > { > return __builtin_arm_crc32w(a,b); > // CHECK: call i32 @llvm.aarch64.crc32w(i32 %a, i32 %b) > } > > -int crc32cw(int a, int b) > +uint32_t crc32cw(uint32_t a, uint32_t b) > { > return __builtin_arm_crc32cw(a,b); > // CHECK: call i32 @llvm.aarch64.crc32cw(i32 %a, i32 %b) > } > > -int crc32d(int a, long b) > +uint32_t crc32d(uint32_t a, uint64_t b) > { > return __builtin_arm_crc32d(a,b); > // CHECK: call i32 @llvm.aarch64.crc32x(i32 %a, i64 %b) > } > > -int crc32cd(int a, long b) > +uint32_t crc32cd(uint32_t a, uint64_t b) > { > return __builtin_arm_crc32cd(a,b); > // CHECK: call i32 @llvm.aarch64.crc32cx(i32 %a, i64 %b) > > Modified: cfe/trunk/test/CodeGen/builtins-arm64.c > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-arm64.c?rev=352463&r1=352462&r2=352463&view=diff > ============================================================================== > --- cfe/trunk/test/CodeGen/builtins-arm64.c (original) > +++ cfe/trunk/test/CodeGen/builtins-arm64.c Tue Jan 29 01:04:03 2019 > @@ -1,4 +1,5 @@ > -// RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone > -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s > +// RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone > -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK > --check-prefix=CHECK-LINUX > +// RUN: %clang_cc1 -triple aarch64-windows -disable-O0-optnone -S -emit-llvm > -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK > --check-prefix=CHECK-WIN > #include <stdint.h> > > void f0(void *a, void *b) { > @@ -16,8 +17,15 @@ unsigned rbit(unsigned a) { > return __builtin_arm_rbit(a); > } > > +// CHECK-WIN: [[A64:%[^ ]+]] = zext i32 %a to i64 > +// CHECK-WIN: call i64 @llvm.bitreverse.i64(i64 [[A64]]) > +// CHECK-LINUX: call i64 @llvm.bitreverse.i64(i64 %a) > +unsigned long rbitl(unsigned long a) { > + return __builtin_arm_rbit64(a); > +} > + > // CHECK: call {{.*}} @llvm.bitreverse.i64(i64 %a) > -unsigned long long rbit64(unsigned long long a) { > +uint64_t rbit64(uint64_t a) { > return __builtin_arm_rbit64(a); > } > > @@ -60,7 +68,7 @@ uint32_t rsr() { > > __typeof__(__builtin_arm_rsr64("1:2:3:4:5")) rsr64(void); > > -uint64_t rsr64() { > +uint64_t rsr64(void) { > // CHECK: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) > return __builtin_arm_rsr64("1:2:3:4:5"); > } > @@ -71,13 +79,17 @@ void *rsrp() { > return __builtin_arm_rsrp("1:2:3:4:5"); > } > > +__typeof__(__builtin_arm_wsr("1:2:3:4:5", 0)) wsr(unsigned); > + > void wsr(unsigned v) { > // CHECK: [[V0:[%A-Za-z0-9.]+]] = zext i32 %v to i64 > // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], > i64 [[V0]]) > __builtin_arm_wsr("1:2:3:4:5", v); > } > > -void wsr64(unsigned long v) { > +__typeof__(__builtin_arm_wsr64("1:2:3:4:5", 0)) wsr64(uint64_t); > + > +void wsr64(uint64_t v) { > // CHECK: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 > %v) > __builtin_arm_wsr64("1:2:3:4:5", v); > } > > > _______________________________________________ > cfe-commits mailing list > cfe-commits@lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
