Is there an obvious way to migrate data from the PL into memory that is mapped into the address space of the PS? Ideally I would use axi_interconnect as shown https://casper-toolflow.readthedocs.io/en/latest/axi4lite_documentation.html
A possible approach is to instantiate axi_dma within the PL , and the PL acts as the master during transfers. But the axi_dma exposes a AXI4-Lite slave port to the PS so that the PS configures and starts the transfers. The receiving raw device would be the memory controller of the PS DDR4. (Presumably the data is accessed later by software via the DMA engine). Another approach would be to expose a single register, and perform this slowly word-by-word (without streaming or bursting.) Is this plausible in CASPER, or are steep changes required? -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/0424800a-035f-447f-92ed-07402b9d0239n%40lists.berkeley.edu.
