Thanks guys :)

On Thu, Nov 19, 2020 at 9:30 AM Jeb Bailey <[email protected]> wrote:

> Check out the Xilinx SSR FFT block in the system generator blockset. It
> will make timing on the ZCU111 in 8x4096 at 512 MHz and is very efficient.
> They also have and HLS SSF FFT that isn’t quite as performant (but has
> public sources. It is in the Vitis IP library on github.
>
> We are using the former in our overlapped PFB.
>
> -Jeb
>
> ——
> Dr. J.I. Bailey, III (Jeb) / Project Scientist
> Mazin Lab <http://web.physics.ucsb.edu/~bmazin/> / Department of
> Physics, UCSB
> jebbailey.com / +1 (734) 389-5143 / skype:spacecolonyone
>
> On Nov 18, 2020, at 10:55 PM, James Smith <[email protected]> wrote:
>
> Hello Morag,
>
> AFAIK, Xilinx's FFT IP block only accepts a single block at a time. I
> think that was a large part of the reason why there's a CASPER FFT in the
> first place - because we needed multiple samples at once.
>
> We have used the Xilinx core in narrowband designs in the past - KAT-7's
> narrowband modes were done that way, after a first "coarse" channelisation
> stage using a Casper PFB, and an async pfb_fir followed by the Xilinx FFT
> block. If you want to pick them apart, they are in here:
> https://github.com/ska-sa/kat7_fpga/tree/master/fengine_oh (warning:
> newer versions of Matlab / mlib_devel may struggle with these old files.
> AVN's narrowband R2 design is somewhat more modern if you have a R2 setup
> handy, they are based on similar principles:
> https://github.com/ska-sa/AVNRoachGateware/tree/devel/source/NarrowBandSpectrometer
> )
>
> Regards,
> James
>
>
> On Wed, Nov 18, 2020 at 5:53 PM Morag Brown <[email protected]> wrote:
>
>> Hi all,
>>
>> Has anyone ever put together a wideband FFT (i.e an FFT that accepts
>> multiple demuxed samples per FPGA clock cycle) using the Xilinx sysgen FFT
>> block? Looking at the docs, it seems the IP core can't be configured to
>> accept multiple parallel inputs (but I could be wrong), so one would need
>> to construct the 2D decomposition of the 1D FFT using Xilinx FFT blocks as
>> primitives.
>>
>> I'm doing some FFT comparisons for my MSc, and would like to include the
>> Xilinx core. I thought it'd be good to check if anyone's already
>> implemented this before embarking on the adventure myself...
>>
>> Morag Brown
>> SARAO
>>
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