Hi Indrajit, User IP clock source should be set to "adc_clk0" Otherwise, your settings looks fine.
When you instantiate a casperfpga.snapadc.SnapAdc() object, the board will use the external sampling clock unless you pass a `ref=<reference_clock_speed>` parameter. Cheers Jack On Wed, 11 Dec 2019 at 10:13, Indrajit Barve <[email protected]> wrote: > Dear Jack / all, > > 1) I am using SMATP15 and feeding sampling clock from outside. I am not > using internal frequency synthesizers(SMATP14) > > My question is the external clock(800 MHz) I am giving from outside via > SMATP15 . In the design clk selection on SNAP yellow block what should I > use ? please see the attached screen-shot. > > 2) FPGA will be running @ 200MHz . > > > Thanks > > *Indrajit Barve* > [email protected] > Radio Astronomy Group > <https://maps.google.com/?q=Radio%20Astronomy%20Group%20> > On Dec 11 2019, at 3:15 pm, Nitish Ragoomundun < > [email protected]> wrote: > > Hi, > > (1.) Yes, my mlib_devel is commit > 98d72edf787575bffa43a797f9723e5c5a569a8c. You can use the methods I > described in the email from December 10th to get it. The repo size is 986 > MiB, and I will not be able to upload this in an email. So, just clone the > mlib_devel repo and checkout to the commit > 98d72edf787575bffa43a797f9723e5c5a569a8c. > > (2.) To make the ADC's work, you need either a 10 or 100 MHz signal at > SMATP14 or a signal at your sampling rate at SMATP15. We used a very stable > 10 MHz signal input at SMATP14, and passeed the ref=10 to > casperfpga.snapadc.SNAPADC( ) in the Python script. I am not sure if it > works the same with clock input at SMATP15, but you can give it a try. > Yes, clocking FPGA at 200 MHz is a good choice as the ADC's will then > interleave the samples and output 4 at each clock. Just one caution based > on your diagram: the User IP Clock Rate should be set to adc0_clk as the > FPGA clock must be aligned to the ADC clock. > > All the best. > Cheers > > > On Wed, Dec 11, 2019 at 10:31 AM Indrajit Barve <[email protected]> > wrote: > > Hi, > Thanks, Thats fine . > 1) Can you share your mlib-devel-master folder. Because the version I do > have don't have the GPIO lib for snap. > 2) If I want to run the spectrometer design at 800 MHz , 3 channel mode. I > will be giving the Sampling clock at SMATP15 > and in the design I keep ADC yellow block sampling as 800MHz and SNAP > board FPGA clocking @ 200 MHz. External clk mode. > > *Indrajit Barve* > [email protected] > Radio Astronomy Group > <https://maps.google.com/?q=Radio%20Astronomy%20Group%20> > > -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAG1GKSnn-%3D8wtWW3UZv29c1qxYO1PsgVJbO35rA02wotF4H9bQ%40mail.gmail.com.
