Hi David and Jack, Interesting. Yes I'm using a 140MHz clock (I'm injecting a 140MHz tone into the adc clock input). I'm sure the FPGA is running at 140MHz because I checked it with fpga.est_brd_clk(). Also, the data duplication occurs for all 16 inputs, so my guess is that is a problem at the adc board level. I'm using the adc_init.rb code with the '--demux 1' flag (I understand that this is the 16 in mode), however I copied this code from someone else, so maybe is an old version. I'll try to use the latest version to see if that is the problem. I'll also try a different (valid) sampling frequency.
Thanks for the suggestions, Franco On Wed, Apr 3, 2019 at 9:07 AM Jack Hickish <[email protected]> wrote: > Hi Franco, > > In addition to Dave's advice-- how are you configuring your board? After > programming the FPGA, you'll need to appropriately configure the ADC to > operate in the right mode. The code seems to be linked here -- > https://casper.ssl.berkeley.edu/wiki/ADC16x250-8_coax_rev_2 > > Cheers > Jack > > On Wed, 3 Apr 2019 at 00:53, Franco <[email protected]> wrote: > >> Hi Casperites, >> >> I'm working in some project that uses a ROACH2 and an adc16x250-8 ADC >> board. When I check the raw data from the ADC using a snapshot block I see >> this weird effect where two consecutive samples have always the same value, >> as shown in this image: >> >> https://my.pcloud.com/publink/show?code=XZMRx67Zpj7XjnkE5PypVuuDCB9Mhu8IJJ37 >> >> According to an ex-coworker, this is the expected behavior of the >> adc16x250-8 board in 16 input mode, because of some constraints in the >> communication between the ADC and the FPGA, the FPGA must run at twice the >> speed to correctly receive the sampled data. However, couldn't find any >> explicit mention of this phenomenon in the CASPER website or mailing list. >> Can someone confirm this is the correct behavior so I can get peace of mind >> :)? >> >> Some info of my test: >> - Board: ROACH2-rev2 >> - ADC: ADC16x250-8 coax rev2 >> - ADC mode: 16 inputs (demux 1, using David Macmahon initalization code) >> - User IP Clock Rate: 140 MHz >> - Actual clock frequency used in the adc board: 140MHz >> >> Thanks, >> >> Franco Curotto >> >> -- >> You received this message because you are subscribed to the Google Groups >> "[email protected]" group. >> To unsubscribe from this group and stop receiving emails from it, send an >> email to [email protected]. >> To post to this group, send email to [email protected]. >> > -- > You received this message because you are subscribed to the Google Groups " > [email protected]" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > To post to this group, send email to [email protected]. > -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected].
