Hi Jack:

I modified the vivado version from 2018.2 to 2018.1 in a file under
cont_microblaze. The compilation is fine and completed. Bitcodes are
generated. I have the UART output as following. My problem is the DHCP
i guess. Looks like the DHCP didn't work. Usually, the led right next
to the RJ45 port should be flashing for some time, but in my case,
that led was so quiet. I have the dhcp running at computer side. Did i
do something wrong?

best
homin

---------------------------------------------------------------
# JAM starting

Built 2019/01/14-17:46-0800 jackh@acme1
mlib_devel-2010-09-20-2405-gb46bd8d264

# Compiled without XADC support

# Compiled without SPI flash support
# Compiled without ICAPE support
using ethernet core  gbe
MAC 0x020304050118

IP 00000000  NM 00000000  GW 00000000

link is UP

On Tue, Jan 15, 2019 at 11:23 AM Jack Hickish <[email protected]> wrote:
>
> Hi CASPERites,
>
> I know a few of you have been playing around with the VCU118 Virtex 
> Ultrascale Plus dev board. For a while the toolflow has been able to compile 
> designs for this board, but without any support for accessing the software 
> registers / brams in the generated bitstream (making the toolflow effectively 
> useless).
>
> The VCU118 branch of mlib_devel -- 
> https://github.com/casper-astro/mlib_devel/tree/vcu118 -- now supports 
> compiling a VCU118 design with an embedded microblaze core, which allows you 
> to talk to the board using the standard casperfpga library.
>
> Note the following caveats --
>
> - use the latest version of casperfpga 
> (https://github.com/casper-astro/casperfpga, currently at commit ee9c43f ) 
> and install the dependencies with `pip install -r requirements.txt` before 
> installing casperfpga with `python setup.py install`. I strongly recommend 
> using a python virtual environment to be sure you are using the right 
> libraries. Note that the dependencies include a custom tftpy **not the one 
> obtained with `pip install tftpy`.
> - casperfpga comms are (currently) only supported through the VCU118's 1GbE 
> RJ45 port
> - You must instantiate a 1GbE yellow block in your design - see 
> https://github.com/casper-astro/mlib_devel/blob/vcu118/jasper_library/test_models/test_onegbe.slx
>  for a simple example
> - You must check the "enable microblaze" checkbox in the VCU118 configuration 
> block.
> - I tested using MATLAB 2017b and Vivado 2018.2. Use other versions of 
> software at your own risk. In particular, other versions of Vivado will 
> probably fail spectacularly.
> - Your VCU118 will attempt to DHCP an IP address on boot. It has the MAC 
> address 02:03:04:05:01:18 . Once DHCP is complete, you should be able to ping 
> the board.
> - Debugging information can be obtained on the VCU's USB UART port, with your 
> serial interface set to 115200 8N1.
> - You must program the bitstream generated by the toolflow manually via JTAG 
> in vivado (the bitstream can be found at 
> <build-directory>/myproj/myproj.runs/impl_1/top.bit). casperfpga's 
> upload_to_ram_and_program command **will NOT work**.
>
> There is still a bunch of work to do to support this board -- for example: 
> supporting writing an image to the onboard flash, getting a unique per-board 
> MAC address, supporting other peripherals (notably 100GbE, which some 
> CASPERites are already working on, and an FMC ADC from ASIAA), etc. etc. But 
> for now, hopefully this zeroth-order support will help with other yellow 
> block development efforts, by allowing you to probe the board without 
> resorting to the joy of the vivado logic analyzer.
>
> Further help always appreciated, and feel free to shout when the above 
> doesn't work for you.
>
> Jack
>
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