Hello everyone, We have a tile of 24 antennas from which we need to acquire data. The central frequency is 327.4 MHz and our working bandwidth is 250 kHz. We need to convert the 24 analogue channels to digital. For this we were thinking about 2x SNAP2 boards operating 12 channels each at 250 MSps. The SNAP FPGA will then filter, decimate and convert the samples to a stream of quadrature samples at a rate of 250 kHz (IQ). Finally the FPGA will need to put the samples in time-stamped packets and ship them out towards a processing server.
We already have one SNAP2 board. Once, Dan Werthimer suggested using the ADC16 board to obtain 16 additional channels. We have a few questions about this implementation: - Does the ADC16 have yellow blocks in the CASPER toolflow to work with? - Can we please have a link to more information about the ADC16 boards in order to learn about the detailed specs, power inputs, clocking inputs, cost, etc. - For a single SNAP2 acquiring 24 channels, will the FPGA be able to cope with the workload for the filtering and packetization part? Thanks. Cheers, Nitish -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected].
