On Fri, Aug 14, 2026 at 4:39 PM Pip Cet <[email protected]> wrote: > > This Makefile: > > ------------------------- > %.o: %.c > gcc -c $< -o $@ > > foo.o: foo.c > echo "stem is $*" > ------------------------- > > results in "make foo.o" producing the output "stem is foo". The same is > true if I omit the first two lines, but not if I run "make -r foo.o" > with just the second rule. > > This seems like a bug to me: the correct output is "stem is ".
No bug. All the behavior you described is intended. > > Note that GCC relies on this behavior: > > https://forge.sourceware.org/gcc/gcc/src/commit/c8545a3143330983e51d913f0a01187258b14510/libgcc/static-object.mk#L30 > > points to this code: > > ---------------------------- > $(base)$(objext): $o $(base).vis > $(gcc_compile) -c $(as_flags-$<) -include $*.vis $< > ---------------------------- > > This means GCC cannot currently be built with "make -r" on some > machines. It doesn't actually use the built-in rules, it only relies on > them to determine what the stem would be according to the rule if it > were to be used. Right. For explicit rules make expands $* to the filename without the suffix in the case of a known suffix. > If this isn't a bug, or a bug we cannot fix at this point because too > much code out there might rely on it, maybe the documentation could > mention it. It does. Read the chapter on automatic variables. regards, Dmitry
