URL: <https://savannah.gnu.org/bugs/?66974>
Summary: Irregular target introduction of unmatched wildcard
include
Group: make
Submitter: None
Submitted: Tue 01 Apr 2025 08:15:07 PM UTC
Severity: 3 - Normal
Item Group: Documentation
Status: None
Privacy: Public
Assigned to: None
Open/Closed: Open
Discussion Lock: Any
Component Version: 4.4.1
Operating System: POSIX-Based
Fixed Release: None
Triage Status: None
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Follow-up Comments:
-------------------------------------------------------
Date: Tue 01 Apr 2025 08:15:07 PM UTC By: Anonymous
I have found a confusing behavior of including a file wildcard pattern that
matches no files which then the pattern itself becomes a target to be built.
```sh
laptop$ cat Makefile
include *.d
%.d: %.c
echo target $@
echo dependencies $^
nothing:
laptop$ ls
Makefile abc.c
laptop$ gmake nothing
echo target *.d
target *.d
echo dependencies abc.c
dependencies abc.c
gmake: Nothing to be done for 'nothing'.
```
The current GNU Make documentation explains that when an include directive
can't find a file, Make will attempt to remake it. However, the behavior with
wildcards isn't sufficiently clear, particularly when no files match a
wildcard
pattern (*.mk) and the pattern itself becomes a target to be built.
Add a brief note to the "Including Other Makefiles" section:
Wildcards in Include Directives
When using wildcards in include directives, if no files match the pattern, GNU
Make will attempt to build the literal wildcard pattern itself as a target. If
a pattern rule exists that could build such a target, Make will execute that
rule with the wildcard pattern as the target name. This can lead to unexpected
behavior in complex Makefiles.
A safer alternative is to use the wildcard function to only include files that
actually exist:
include $(wildcard *.mk)
This ensures that Make will only include existing files matching the pattern
and won't attempt to build the pattern itself as a target.
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