URL:
<http://savannah.gnu.org/bugs/?47913>
Summary: newlines lost with $(foreach)
Project: make
Submitted by: opk
Submitted on: Fri 13 May 2016 04:41:26 PM CEST
Severity: 3 - Normal
Item Group: Bug
Status: None
Privacy: Public
Assigned to: None
Open/Closed: Open
Discussion Lock: Any
Component Version: SCM
Operating System: Any
Fixed Release: None
Triage Status: None
_______________________________________________________
Details:
I tried the 4.1.90 release candidate with my Makefiles and found a problem due
to it behaving differently to previous releases with regard to newlines being
lost from a variable when using $(foreach).
Simplifying things a lot, what I have is roughly along these lines:
define FILEDEPS
File.cpp: File.h
Other.cpp: Other.h
endef
here = here
ifdef FILEDEPS
$(eval $(foreach dep,$(FILEDEPS),$(or $(filter :,$(dep)),$(abspath
$(here)/$(dep)
))))
endif
To put this into context, I use a non-recursive setup where a small Makefile
in each individual directory contains definitions for that directory's
contents and then includes a complex common makefile which defines all the
rules and includes all the other Makefiles. So this allows certain extra file
depenencies to be defined without specifying the directory. here is actually
set with something like the following so that it points to the directory of
the current directory specific
Makefile:
here := $(dir $(lastword $(filter-out %.d %.D %.mk %/config.inc $(lastword
$(MAKEFI
LE_LIST)), $(MAKEFILE_LIST))))
With 4.1.90, I get a "multiple target patterns" error. If you change $(eval)
for $(info), current releases of GNU make show the two file dependencies. With
4.1.90, it has wrapped them onto a single line.
Is this an intentional change, a bug or just an implementation quirk that I
shouldn't have relied on?
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