Follow-up Comment #1, bug #46013 (project make):
Simplified example:
#!/bin/bash
#
exec gmake --warn-undefined-variables -f "$0" "$@"
$(warning Global 1: TEST == ${TEST})
# I took the liberty of adding "export"
export override TEST :=${TEST}.
$(warning Global 2: TEST == ${TEST})
1 2:
$(warning From target $@: TEST == ${TEST})
$(if $(filter 1,$@),@${MAKE} -f $(firstword ${MAKEFILE_LIST}) 2
# Executed like this you get ".." in the 2nd invocation:
~ example.sh
# Executed like this the command-line variable cannot be
# overridden for recursive make calls; TEST is always "x."
~ example.sh TEST=x
# Executed like this you get "x.." in the 2nd invocation:
~ TEST=x example.sh
~ example.sh -e TEST=x
I'm of the opinion this /not/ unexpected behavior. The documentation says
nothing about overriding for recursive make invocations when you use the
"override" keyword. Furthermore, it's probably better practice to explicitly
pass along a MAKE variable to recursive make instances instead of it being
implicit, otherwise tracking down a bug related to it could be more
problematic.
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