On Thu, Oct 7, 2010 at 9:22 AM, David Highley <dhigh...@highley-recommended.com> wrote: ... > Let us just cut to the essence of the issue we are running into, how do > target prerequisites get processed in version 3.81 of make? > > Example: > $(LIBRARY): $(INF_DIST_SVCS_OBJS) > > $(INF_DIST_SVCS_OBJS): $(DIRS) > > $(DIRS): > > .PHONY: $(DIRS) > > With parallel building how does the macro $(INF_DIST_SVCS_OBJS) get > evaluated before the target $(DIRS) is done? Is there a method to stop > this other than turning parallel building off?
Have you read the info pages section "How `make' Reads a Makefile"? In it, it explains that variables in targets and prerequisite lists are expanded immediately when the rule is read during the parsing of the Makefile. So, *before any targets have been built*, $(INF_DIST_SVCS_OBJS) will be expanded twice during the parsing of the above Makefile snippet, once when the $(LIBRARY) rule is parsed and once when the $(INF_DIST_SVCS_OBJS) rule is parsed. The -j option has no effect on that, so I don't understand your last question above. Or are you saying that this makefile is part of a recursive make setup, so that it might be read multiple times, the earlier of which could affect the latter of which? Philip Guenther _______________________________________________ Bug-make mailing list Bug-make@gnu.org http://lists.gnu.org/mailman/listinfo/bug-make
