Follow-up Comment #4, bug #27609 (project make):
By the way, this is quite bad. The behavior happens even if I have an
explicit rule like this:
foo.o: foo.c
If there is a foo.y, foo.c is clobbered, even though foo.c exists.
This is so retarded.
The search for the prerequisite of foo.o must stop when foo.c is found.
I can understand that the search, upon not finding foo.c, might go on to try
other suffixes like foo.y.
That is to say, the rule should be about making a foo.o from a foo.y, not
making a foo.c from a foo.y!!!
Yes, sure. Okay. If I have a Makefile like this:
program: foo.o
and the only file in the directory is foo.y (and no foo.c), then go ahead and
run yacc to make foo.c from foo.y, and compile foo.c to foo.o.
Actually we don't need foo.c in that case. We just need some temporary name.
The rule has to handle the complete job of translating .y to .o:
$(YACC) $(YACCFLAGS) foo.y
mv y.tab.c <temporary_name>
$(CC) $(CFLAGS) -c <temporary_name> -o foo.o
Now this actually makes sense. If there is no .c file, why not infer that .y
is the prerequisite for a .o?
Just don't involve a foo.c file in the inference chain.
<temporary_name> can be based on foo.y somehow (just not in a naive way like
foo.c!) Even if it was foo.y.tab.c, or foo.y.out, or whatever.
There could even be an implicit rule which, given a foo.o, finds the
prerequisite foo.y.tab.c.
It's less likely that someone would write a file by hand called foo.y.tab.c,
than foo.c.
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