This is not really a bug in GNU make but an update to your the practice you
recommend for Generating Prerequisites Automatically in section 4.14 of GNU
make manual
Your recomendation is:
-------------- quote ----------------
Here is the pattern rule to generate a file of prerequisites (i.e., a
makefile) called `name.d' from a C source file called `name.c':
%.d: %.c
@set -e; rm -f $@; \
$(CC) -M $(CPPFLAGS) $< > $@.$$$$; \
sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \
rm -f $@.$$$$
-------------- end quote ----------------
The problem with it follows:
Background:
If I have a c-source files like this:
-------- code -----------------
// ex.c
#include "ex1.h"
...
// ex1.h
#include "ex2.h"
// ex2.h
...
-------- end code -----------------
All is working fine, and dependecy makefile is generated properly, containing
information that both ex.o and ex.d depend on ex.c, ex1.h and ex2.h
Problem:
If later I change my source code and remove ex2.h from my project ( also from
ex1.h ), inspite of all my source is correct, make will fail with message like
make: *** No rule to make target `ex2.h', needed by `ex.d'. Stop.
because ex.d is really still depending on ex2.h
Solution:
I suggest creating last-resort rule in generated makefile that will
regenerate makefile itself
%.d: %.c
@set -e; rm -f $@; \
$(CC) -M $(CPPFLAGS) $< > $@.$$$$; \
sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \
rm -f $@.$$$$
echo ".DEFAULT: ; rm $@" >> $@
Dixi =)
--
Sincerely yours
Peter Kerzum
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