In the "Target-specific Variable Values" section of the gmake manual
(http://www.gnu.org/manual/make-3.79.1/html_node/make_70.html#SEC69)
it is noted that " when you define a target-specific variable, that
variable value is also in effect for all prerequisites of this target".
However, this does not work for built-in rules, as is demonstrated by
the following example:
# Example Makefile
try: OBJECT = try.o
try: $(OBJECT)
cc -o $@ $<
When used with make version 3.79.1 on a FreeBSD 4.5-STABLE (i386) system
this results in:
gmake
cc -o try
cc: No input files specified
gmake: *** [try] Error 1
If the target-specific OBJECTS variable line is changed to
"OBJECT = try.o" then GNU make works as expected:
gmake
cc -c -o try.o try.c
cc -o try try.o
It seems that the presence of a target-specific variable in the
dependency list of the target prevents the built-in rule from being used.
I tried providing the typical pattern rule:
%.o: %.c
cc -c $<
This works as expected when $(OBJECT) is a simple variable. But, here
too, when $(OBJECT) is a target-specific variable this prevents the
pattern rule from being used.
Here is an "interesting" work-around:
# Work-around Makefile
try: SOURCE = try.c
try: OBJECT = $(SOURCE:%.c=%.o)
try: obj
$(CC) -o $@ $(OBJECT)
obj:
$(CC) -c $(SOURCE)
This results in the expected:
gmake
cc -c try.c
cc -o try try.o
--
Bradford Castalia
Senior Systems Analyst
Planetary Image Research Laboratory
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