hello,
I'm not sure whether the following reflects a bug,
or just my misunderstanding of the way make works...
I'd like to build a library 'libFoo.a' out of files
distributed over a couple of subdirectories:
src/Foo/Bar/bar.cc
src/Foo/Baz/baz.cc
...
and src/Foo/Makefile looks so:
------
SRC
:= Bar/bar.cc Baz/baz.cc
OBJ
:= $(patsubst %.cc, %.o, $(SRC))
TARGET
:= libFoo.a
all:
$(TARGET)
%.o: %.cc
touch $@
$(TARGET):
$(OBJ)
touch $(TARGET)
------
so far all is fine. However, I'm now generating the Makefile
from Makefile.in, and the generated Makefile is in a separate
build tree, so the new Makefile is modified to refer to the
src files in terms of a $(srcdir) variable (generated from
configure):
------
srcdir
:= ..
SRC
:= Bar/bar.cc Baz/baz.cc
OBJ
:= $(patsubst %.cc, %.o, $(SRC))
TARGET
:= libFoo.a
all:
$(TARGET)
%.o: $(srcdir)/%.cc
touch $@
$(TARGET):
$(OBJ)
touch $(TARGET)
------
invoking 'make' now results in the error message
'No rule to make target `Bar/bar.o', needed by `libFoo.a''
Just to make sure that it's not a wrong variable, I add
a 'more explicit' rule to the end of the Makefile:
------
Bar/%.o: $(srcdir)/Bar/%.cc
touch $@
Baz/%.o: $(srcdir)/Baz/%.cc
touch $@
------
and it works again.
It seems this is a bug in the pattern matching.
I'm running make version 3.78.1.
Any help is highly appreciated !
Regards,
Stefan
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