This is not a bug. make uses whatever target comes first as the
default target. Try:
# force my default target
all : $(whatever)
# now do includes
include makefiles
# now do local rules
...
tim
PS: you might want to upgrade your version of make. It won't change
this (correct) behavior, but there have been many improvements.
On Tue, Sep 12, 2000 at 03:29:46PM +0100, Olivier Durand wrote:
> Hello,
>
> I am currently using gmake V3.77 and experience problems with including
> makefiles.... I hope you can help me on this one...
>
> I have two solution here: I can either use the include directive or the
> MAKEFILES environment variable.
> The include directive works fine but redefines the goal of my makefile
> to the first target of the included file (if there is one...) since I
> would like to put all my inlcudes at the begining of the file.
>
> MAKEFILES is better in this respect as the default goal is never taken
> from one of these makefiles. However, I need to set MAKEFILES "outside"
> the makefile (i.e. in my current environment) which I find a bit
> "hacky"... As specified in the documentation MAKEFILE is ONLY useful for
> recursive makefiles but this is not my intention as I want to work on a
> flat level (i.e. each entity should build independently).
>
> What shall I do then?....
>
> Looking forward to hear from you.
>
> Many Thanks,
>
> Olivier
>
> PS: Find attached a simple example illustrating my problem....
>
>
> # Note...
> # This file contains all my generic implicit/explicit rules as well as path
> # etc...
> # I don't want the first rule of this makefile to be taken as a goal when
> # included in other makefile.
> # The implicit rules defined in this makefile may be overridden in makefiles
> # including this one, hence the include has to be performed at the beginning
> # of the makefile...
>
> MY_VAR = Hi
>
>
> generic_rule1:
> @echo I Don't want this rule to be my goal!
>
>
> generic_rule2:
> @echo I would like this to work badly!....
>
>
> MAKEFILES= Makefile.inc
> #include Makefile.inc
>
>
> My_Goal:
> @echo $(MY_VAR)
> @echo If it worked, there would be two lines printed on the screen...
> $(MAKE) -f Makefile.test
>
>
> generic_rule2:
> @echo This rule overrides the one defined in Makefile.inc....
>
>
>
>
>
> # This makefile illustrate recursivity.
> # Because MAKFILES is defined in parent process
> # make should include "Makefile.inc" in this file...
>
> Test_target:
> @echo If MAKEFILES worked, something would appear here: $(MY_VAR)
