Hi,
i think i found a bug:
In a project directory i have the subdirs "source" and "object"
and a "Makefile". In "source" are the files "main.c" and "fct.c".
+ source
| |--main.c
| \--fct.c
+ object
+ Makefile
A Makefile that doesn't work:
################################
SRC = main.c \
fct.c
#OBJS = $(patsubst %.c,object/%.o,$(SRC))
show:
@echo $(OBJS)
all: $(OBJS)
gcc -o program $^
$(OBJS) : object/%.o : source/%.c
gcc -c $< -o $@
OBJS = $(patsubst %.c,object/%.o,$(SRC))
################################
A Makefile that works:
################################
SRC = main.c \
fct.c
OBJS = $(patsubst %.c,object/%.o,$(SRC))
show:
@echo $(OBJS)
all: $(OBJS)
gcc -o program $^
$(OBJS) : object/%.o : source/%.c
gcc -c $< -o $@
#OBJS = $(patsubst %.c,object/%.o,$(SRC))
################################
The difference is the position where i define "OBJS".
In the first case i define it at the end of the file, in the latter
at the beginning.
I think $(OBJS) should expand recursively, i use a
normal "=" to give it it's value.
I was able to reproduce this behaviour with GNU make 3.78.1
for Linux and GNU make 3.79 in cygwin.
Is this a bug?
Can you reproduce it?
Don't hesitate to write me if you need more information, i'd be glad
to help.
Best regards,
Torsten.
http://www.s.netic.de/tmohr/linux.html
