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Hello GNU make-gurus,
I'm
using the following GNU make version:
GNU Make version 3.79, by Richard Stallman and
Roland McGrath.Built for i686-pc-linux-gnu.
I am trying to port a recursive Makefile-structure
designed for the
SunOS5 make utility to use
the GNU make . This implies that I have rather complex pattern matching
rules
that dynamically builds the prerequisites for the
target. In the original Sun Makefile this
looks as follows:
my_lib_OBJS = foo.o fie.o
$(LIBRARY:%=%.a):
$$($$(@F:%.a=%)_OBJS:%.o=%.o)
$(LD) $(LDFLAGS)
$($(TARGETNAME)_LDFLAGS) -r -o $@ etc....
This rule builds a shared library depending on a number of
object files. The prerequisite for the object files is
obtained by:
1. Constructing the name of a
<library>_OBJS variable defined in makefile.
2. Evaluating the
constructed variable $(<library>_OBJS) which gives the list of the object
files.
For example:
If make is invoked as `make my_lib´ this would
ideally expand to
my_lib.a: $(my_lib_OBJS) and finally when my_libs_OBJS is
evaluated to
my_lib.a: foo.o fie.o
As can be seen the Sun make allows usage of automatic
variables in the prerequisite part of the rule as well as
evaluation of composed variables.
After reading the documentation for GNU make and a number of
fruitless attempts it seems that GNU make is
not allowing this. My question is:
1. Shall GNU make support the same features?
2. If not, is there a way workaround this?
I would be very grateful for an answer to these
questions.
Regards
Ulf Hägglund
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