[Bug binutils/30495] [libopcodes][riscv] ori x0, xn, imm decoded as incorrect instruction class causing gdb sim to terminate

[shank.vijay at yandex dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30495

vijay Shankar <shank.vijay at yandex dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |shank.vijay at yandex dot com

--- Comment #1 from vijay Shankar <shank.vijay at yandex dot com> ---
The issue is observed because zicbop instructions use same encoding as or 0x0
0x1 0x3 correspond to three prefetch instructions
https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc real
solution would require to impliment cmo instructions in gdb-sim.

However there is a workaround solution

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 41973d9dd06..f3b26348d7f 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1365,6 +1365,9 @@ void step_once (SIM_CPU *cpu)
       /* Does the opcode match?  */
       if (! op->match_func || ! op->match_func (op, iw))
        continue;
+      /*FIXME:Ignoring ZICBOP for now but remove when support is added*/
+      if(op->insn_class == INSN_CLASS_ZICBOP)
+       continue;
       /* Is this a pseudo-instruction and may we print it as such?  */
       if (op->pinfo & INSN_ALIAS)
        continue;

this seem to fix the issue. not sure who to add to cc since there seem to be no
maintainers for gdb-sim?

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