https://sourceware.org/bugzilla/show_bug.cgi?id=29844
--- Comment #3 from H.J. Lu <hjl.tools at gmail dot com> ---
This is introduced by
commit c9f5b96bdab031e9520d98e01ee1bef1ffd3b961
Author: Jan Beulich <jbeul...@suse.com>
Date: Thu Nov 24 09:34:52 2022 +0100
x86: correct handling of LAR and LSL
In Intel64 manual, both LAR and LSL have NOTES:
* For all loads (regardless of destination sizing), only bits 16-0 are used.
Other bits are ignored.
In AMD64 manual, both LAR and LSL have
LAR/LSL reg16, reg/mem16
LAR/LSL reg32, reg/mem16
LAR/LSL reg64, reg/mem16
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