https://sourceware.org/bugzilla/show_bug.cgi?id=29342
Nelson Chu <nelsonc1225 at sourceware dot org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |RESOLVED
CC| |nelsonc1225 at sourceware dot
org
Resolution|--- |FIXED
--- Comment #5 from Nelson Chu <nelsonc1225 at sourceware dot org> ---
Marked as resolved and fixed since the following commit,
commit 48525554d5222d98953202b9252ff65fdead58a4
Refs: gdb-12-branchpoint-1830-g48525554d52
Author: Tsukasa OI <research_tra...@irq.a4lg.com>
AuthorDate: Sat Aug 27 00:11:00 2022 +0000
Commit: Nelson Chu <nel...@rivosinc.com>
CommitDate: Fri Sep 2 12:06:27 2022 +0800
RISC-V: PR29342, Fix RV32 disassembler address computation
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an
incorrectly sign-extended address is produced when printing. This commit
fixes this by fitting an address into a 32-bit value on RV32.
Besides, H. Peter Anvin discovered that we have wrong address computation
for JALR instruction (the initial bug is back in 2018). This commit also
fixes that based on the idea of Palmer Dabbelt.
gas/
pr29342
* testsuite/gas/riscv/lla32.d: Reflect RV32 address computation
fix.
* testsuite/gas/riscv/dis-addr-overflow.s: New testcase.
* testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.
opcodes/
pr29342
* riscv-dis.c (maybe_print_address): Fit address into 32-bit on
RV32.
(print_insn_args): Fix JALR address by adding EXTRACT_ITYPE_IMM.
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