https://sourceware.org/bugzilla/show_bug.cgi?id=25202
Bug ID: 25202
Summary: objcopy --verilog-data-width doesn't respect target's
endianness
Product: binutils
Version: 2.33
Status: UNCONFIRMED
Severity: normal
Priority: P2
Component: binutils
Assignee: unassigned at sourceware dot org
Reporter: olof.kindgren at gmail dot com
Target Milestone: ---
I just tried binutils 2.33.1 compiled for riscv32-unknown-elf to test
https://sourceware.org/bugzilla/show_bug.cgi?id=19921. Unfortunately it doesn't
match what I was expecting to see.
Problem is that it will always use big endian output since (I think) the
bfd_target for verilog has BFD_ENDIAN_UNKNOWN. I was expecting it to use the
endianness of the source architecture.
I got around it by setting target byte order of the verilog_vec bfd_target to
BFD_ENDIAN_LITTLE but I don't have enough experience with binutils to see where
the correct fix should be.
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