https://sourceware.org/bugzilla/show_bug.cgi?id=24226
Bug ID: 24226
Summary: Need advise on the binutils problem that generating
wrong instruction like lw a3,-2048(a5) on RISC-V
backend
Product: binutils
Version: unspecified
Status: UNCONFIRMED
Severity: critical
Priority: P2
Component: ld
Assignee: unassigned at sourceware dot org
Reporter: liuyingying19 at huawei dot com
Target Milestone: ---
Created attachment 11610
--> https://sourceware.org/bugzilla/attachment.cgi?id=11610&action=edit
test case
Hello experts,
We are having the similar problem described in below:
https://groups.google.com/a/groups.riscv.org/forum/#!msg/sw-dev/KnziiZtEJNo/Jg4YBJ56CgAJ
In our testcase, we are using the option –mcmodel = medlow and
-mexplicit_relocs, but we got the similar problem that binutils will generate
wrong instruction like lw a3,-2048(a5).
When compiled to .S file, the result is correct:
lui a5,%hi(g_3030)
lw a4,%lo(g_3030)(a5)
srli a4,a4,8
lw a3,%lo(g_3030+4)(a5)
After link, the result is not correct:
1db2a: 0002a7b7 lui a5,0x2c
1db2e: 7fc7a703 lw a4,2044(a5) # 2c7fc
<g_3030>
1db32: 8321 srli a4,a4,0x8
1db34: 8007a683 lw a3,-2048(a5)
The result of %lo(g_3030+4) should be 2044 + 4 = 2048, but the value 2048
overflowed the 12 bit signed value, turn to -2048 and cause problem.
The workaround to not use –mexplicit_relocs (discussed in
https://groups.google.com/a/groups.riscv.org/forum/#!msg/sw-dev/KnziiZtEJNo/Jg4YBJ56CgAJ
)would not work for us. It enlarges the code size for 10-20%. Is there any
advice to fix this problem without bring too much effect on the code size?
Best wishes,
Grace
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