https://sourceware.org/bugzilla/show_bug.cgi?id=20067
Bug ID: 20067
Summary: GAS generates an illegal instruction for the 'FLD'
pseudo instruction
Product: binutils
Version: 2.27 (HEAD)
Status: NEW
Severity: normal
Priority: P2
Component: gas
Assignee: unassigned at sourceware dot org
Reporter: chuazl at comp dot nus.edu.sg
Target Milestone: ---
Processor : Marvell PJ4Bv7 Processor rev 2 (v7l)
Features : swp half thumb fastmult vfp edsp vfpv3 tls
CPU implementer : 0x56
CPU architecture: 7
CPU variant : 0x2
CPU part : 0x584
CPU revision : 2
Assembling 'FLDD D11, =0' with -mfpu=vfpv3 produces 'VMOV.I64 D11, #0'.
Executing it on the CPU results in an illegal operation.
VMOV (Immediate) VMOV.I64 is a NEON instruction and specifying -mfpu=vfpv3
specifies that the coprocessor does not support NEON, however GAS still emits
the vmov.i64 instruction.
Details:
md assembled is called with the following arguments: md_assemble (str=0x162982
"fldd D11,=0")
opcode now contains the result of opcode_lookup("fldd D11, =0)
*Note, this will pass all the constraint test since the requirements of 'fldd'
is just vfp
aencode of opcode is called which is actually do_vfp_dp_ldst().
do_vfp_dp_ldst() calls encode_arm_cp_address() which in turn calls
move_or_literal_pool().
This is where the problem occurs, neon_cmode_for_move_imm() is called if the
type is a CONST_VEC without any checks for NEON support which results in the
VMOV.I64 instruction to be generated.
Workaround patch:
As a workaround, I've added in the feature check in the else if statement, if
the fpu doesn't support NEON, use the default literal-pool load, not sure of
the correctness.
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