http://sourceware.org/bugzilla/show_bug.cgi?id=15623
Bug ID: 15623
Summary: smc + condition code is not enforced to be last
instruction in IT block
Product: binutils
Version: 2.24 (HEAD)
Status: NEW
Severity: normal
Priority: P2
Component: gas
Assignee: unassigned at sourceware dot org
Reporter: [email protected]
Thumb SMC instruction needs to be the last instruction in an IT block just like
e.g. BXJ. However this is not enforced for implicit IT blocks
(-mimplicit-it=thumb) like it is for e.g. with BXJ.
Using GNU assembler (GNU Binutils) 2.23.52.20130420:
$ cat gas.s
.text
.thumb
.syntax unified
BXJCC R4
SWICC #5
$ arm-unknown-eabi-as -mcpu=cortex-a8 -mimplicit-it=thumb -o gas.o gas.s
$ arm-unknown-eabi-objdump -d gas.o
/tmp/gas.o: file format elf32-littlearm
Disassembly of section .text:
00000000 <.text>:
0: bf38 it cc
2: f3c4 8f00 bxjcc r4
6: bf38 it cc
8: df05 svccc 5
=> note two IT instructions as bxj needs to be the last instruction of
an IT block.
Same test for SMC:
$ cat gas2.s
.text
.thumb
.syntax unified
SMCCC #5
SWICC #5
$ arm-unknown-eabi-as -mcpu=cortex-a8 -mimplicit-it=thumb -o gas2.o gas2.s
$ arm-unknown-eabi-objdump -d gas2.o
/tmp/gas.o: file format elf32-littlearm
Disassembly of section .text:
00000000 <.text>:
0: bf3c itt cc
2: f7f5 8000 smccc #5
6: df05 svccc 5
However I expect rather to see:
00000000 <.text>:
0: bf38 it cc
2: f7f5 8000 smccc #5
6: bf38 it cc
8: df05 svccc 5
I.e. two IT instructions.
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