http://sourceware.org/bugzilla/show_bug.cgi?id=12608
Summary: TLS relocations issues on alpha
Product: binutils
Version: 2.21
Status: NEW
Severity: normal
Priority: P2
Component: ld
AssignedTo: unassig...@sources.redhat.com
ReportedBy: aurel...@aurel32.net
Host: alphaev68-unknown-linux-gnu
Target: alphaev68-unknown-linux-gnu
Build: alphaev68-unknown-linux-gnu
Some TLS glibc tests fail on alpha when built with gcc -mtune=ev5 or later CPU.
Digging into the issues, it seems the problem comes from the linker.
The problem affects tst-tlsmod7.c and tst-tlsmod8.c. When built with
-mtune=ev5, some instructions are re-ordered, which seems to confuse ld. Let's
give the example of tst-tlsmod7. I have attached the corresponding source code
to this bug report, it's possible to build the .so with "gcc -shared
tst-tlsmod7.s -o tst-tlsmod7.so". The difference at the source level causing
the issue between -mtune=ev4 and -mtune=ev5 is the following:
--- tst-tlsmod7.ev4.s
+++ tst-tlsmod7.ev5.s
@@ -429,8 +429,8 @@
cmpeq $1,27,$1
beq $1,$L36
.loc 1 26 0
- lda $16,local1($29) !tlsldm!29
ldq $27,__tls_get_addr($29) !literal!29
+ lda $16,local1($29) !tlsldm!29
jsr $26,($27),__tls_get_addr !lituse_tlsldm!29
ldah $29,0($26) !gpdisp!31
ldah $0,local1($0) !dtprelhi
When looking at the corresponding .o, the difference is still the same:
--- tst-tlsmod7.ev4.o
+++ tst-tlsmod7.ev5.o
@@ -295,10 +295,10 @@
318: 08 00 21 a4 ldq t0,8(t0)
31c: a1 75 23 40 cmpeq t0,0x1b,t0
320: 21 00 20 e4 beq t0,3a8 <check1+0x178>
- 324: 00 00 1d 22 lda a0,0(gp)
- 324: TLSLDM local1
- 328: 00 00 7d a7 ldq t12,0(gp)
- 328: ELF_LITERAL __tls_get_addr
+ 324: 00 00 7d a7 ldq t12,0(gp)
+ 324: ELF_LITERAL __tls_get_addr
+ 328: 00 00 1d 22 lda a0,0(gp)
+ 328: TLSLDM local1
32c: 00 40 5b 6b jsr ra,(t12),330 <check1+0x100>
32c: LITUSE .text+0x5
32c: HINT __tls_get_addr
When looking at the corresponding .so, the difference has now changed, probably
due to a relocation issue in the linker:
--- tst-tlsmod7.ev4.so
+++ tst-tlsmod7.ev5.so
@@ -744,7 +744,7 @@
d38: 08 00 21 a4 ldq t0,8(t0)
d3c: a1 75 23 40 cmpeq t0,0x1b,t0
d40: 21 00 20 e4 beq t0,dc8 <check1+0x178>
- d44: 58 80 1d a6 ldq a0,-32680(gp)
+ d44: 58 80 7d a7 ldq t12,-32680(gp)
d48: 00 00 fe 2f unop
d4c: 9e 00 00 00 rduniq
d50: 00 04 00 42 addq a0,v0,v0
The value is now loaded into t12 instead of a0, which gives a segfault when
this address is used a bit later.
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