Disassembler for i386/x86_64 (i386-dis.c) in objdump prints incorrect bytemodes in Intel syntax. At least, 27 SIMD instructions seem incorrect.
% objdump -v GNU objdump (GNU Binutils) 2.17.50.20070620 Copyright 2007 Free Software Foundation, Inc. This program is free software; you may redistribute it under the terms of the GNU General Public License. This program has absolutely no warranty. % cat simd.s .text .byte 0xf2, 0x0f, 0xd0, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x66, 0x0f, 0x2f, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x0f, 0x2f, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0xf3, 0x0f, 0xe6, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0xf2, 0x0f, 0xe6, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x0f, 0x5a, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0xf3, 0x0f, 0x5b, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0xf2, 0x0f, 0x7c, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0xf3, 0x0f, 0x7f, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0xf3, 0x0f, 0x6f, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x66, 0x0f, 0x17, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x66, 0x0f, 0x16, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x0f, 0x17, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x0f, 0x16, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x66, 0x0f, 0x13, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x66, 0x0f, 0x12, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x0f, 0x13, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x0f, 0x12, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0xf3, 0x0f, 0x16, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0xf3, 0x0f, 0x12, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0xf3, 0x0f, 0x70, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x90, 0xf2, 0x0f, 0x70, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x90, 0x0f, 0x60, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x0f, 0x62, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x0f, 0x61, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x66, 0x0f, 0x2e, 0x0d, 0x78, 0x56, 0x34, 0x12 .byte 0x0f, 0x2e, 0x0d, 0x78, 0x56, 0x34, 0x12 % as -o simd.o simd.s % objdump -d -M intel --section=LC_SEGMENT.__TEXT.__text simd.o simd.o: file format mach-o-le Disassembly of section LC_SEGMENT.__TEXT.__text: 0000000000000000 <LC_SEGMENT.__TEXT.__text>: 0: f2 0f d0 0d 78 56 34 addsubps xmm1,QWORD PTR ds:0x12345678 7: 12 8: 66 0f 2f 0d 78 56 34 comisd xmm1,XMMWORD PTR ds:0x12345678 f: 12 10: 0f 2f 0d 78 56 34 12 comiss xmm1,XMMWORD PTR ds:0x12345678 17: f3 0f e6 0d 78 56 34 cvtdq2pd xmm1,DWORD PTR ds:0x12345678 1e: 12 1f: f2 0f e6 0d 78 56 34 cvtpd2dq xmm1,QWORD PTR ds:0x12345678 26: 12 27: 0f 5a 0d 78 56 34 12 cvtps2pd xmm1,XMMWORD PTR ds:0x12345678 2e: f3 0f 5b 0d 78 56 34 cvttps2dq xmm1,DWORD PTR ds:0x12345678 35: 12 36: f2 0f 7c 0d 78 56 34 haddps xmm1,QWORD PTR ds:0x12345678 3d: 12 3e: f3 0f 7f 0d 78 56 34 movdqu DWORD PTR ds:0x12345678,xmm1 45: 12 46: f3 0f 6f 0d 78 56 34 movdqu xmm1,DWORD PTR ds:0x12345678 4d: 12 4e: 66 0f 17 0d 78 56 34 movhpd XMMWORD PTR ds:0x12345678,xmm1 55: 12 56: 66 0f 16 0d 78 56 34 movhpd xmm1,XMMWORD PTR ds:0x12345678 5d: 12 5e: 0f 17 0d 78 56 34 12 movhps XMMWORD PTR ds:0x12345678,xmm1 65: 0f 16 0d 78 56 34 12 movhps xmm1,XMMWORD PTR ds:0x12345678 6c: 66 0f 13 0d 78 56 34 movlpd XMMWORD PTR ds:0x12345678,xmm1 73: 12 74: 66 0f 12 0d 78 56 34 movlpd xmm1,XMMWORD PTR ds:0x12345678 7b: 12 7c: 0f 13 0d 78 56 34 12 movlps XMMWORD PTR ds:0x12345678,xmm1 83: 0f 12 0d 78 56 34 12 movlps xmm1,XMMWORD PTR ds:0x12345678 8a: f3 0f 16 0d 78 56 34 movshdup xmm1,DWORD PTR ds:0x12345678 91: 12 92: f3 0f 12 0d 78 56 34 movsldup xmm1,DWORD PTR ds:0x12345678 99: 12 9a: f3 0f 70 0d 78 56 34 pshufhw xmm1,DWORD PTR ds:0x12345678,0x90 a1: 12 90 a3: f2 0f 70 0d 78 56 34 pshuflw xmm1,QWORD PTR ds:0x12345678,0x90 aa: 12 90 ac: 0f 60 0d 78 56 34 12 punpcklbw mm1,QWORD PTR ds:0x12345678 b3: 0f 62 0d 78 56 34 12 punpckldq mm1,QWORD PTR ds:0x12345678 ba: 0f 61 0d 78 56 34 12 punpcklwd mm1,QWORD PTR ds:0x12345678 c1: 66 0f 2e 0d 78 56 34 ucomisd xmm1,XMMWORD PTR ds:0x12345678 c8: 12 c9: 0f 2e 0d 78 56 34 12 ucomiss xmm1,XMMWORD PTR ds:0x12345678 Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A, http://www.intel.com/products/processor/manuals/index.htm It's written: ADDSUBPS - Packed Single-FP Add/Subtract Opcode Instruction 64-Bit Mode Compat/Leg Mode F2 0F D0 /r ADDSUBPS xmm1, Valid Valid xmm2/m128 The second operand is XMM register or 128-bit memory. Hence, the bytemode of addsubps should be XMMWORD, not QWORD. As the same way, comisd should have QWORD, not XMMWORD. All of the instructions above are incorrect bytemodes. The expected result should be: 0000000000000000 <LC_SEGMENT.__TEXT.__text>: 0: f2 0f d0 0d 78 56 34 addsubps xmm1,XMMWORD PTR ds:0x12345678 7: 12 8: 66 0f 2f 0d 78 56 34 comisd xmm1,QWORD PTR ds:0x12345678 f: 12 10: 0f 2f 0d 78 56 34 12 comiss xmm1,DWORD PTR ds:0x12345678 17: f3 0f e6 0d 78 56 34 cvtdq2pd xmm1,QWORD PTR ds:0x12345678 1e: 12 1f: f2 0f e6 0d 78 56 34 cvtpd2dq xmm1,XMMWORD PTR ds:0x12345678 26: 12 27: 0f 5a 0d 78 56 34 12 cvtps2pd xmm1,QWORD PTR ds:0x12345678 2e: f3 0f 5b 0d 78 56 34 cvttps2dq xmm1,XMMWORD PTR ds:0x12345678 35: 12 36: f2 0f 7c 0d 78 56 34 haddps xmm1,XMMWORD PTR ds:0x12345678 3d: 12 3e: f3 0f 7f 0d 78 56 34 movdqu XMMWORD PTR ds:0x12345678,xmm1 45: 12 46: f3 0f 6f 0d 78 56 34 movdqu xmm1,XMMWORD PTR ds:0x12345678 4d: 12 4e: 66 0f 17 0d 78 56 34 movhpd QWORD PTR ds:0x12345678,xmm1 55: 12 56: 66 0f 16 0d 78 56 34 movhpd xmm1,QWORD PTR ds:0x12345678 5d: 12 5e: 0f 17 0d 78 56 34 12 movhps QWORD PTR ds:0x12345678,xmm1 65: 0f 16 0d 78 56 34 12 movhps xmm1,QWORD PTR ds:0x12345678 6c: 66 0f 13 0d 78 56 34 movlpd QWORD PTR ds:0x12345678,xmm1 73: 12 74: 66 0f 12 0d 78 56 34 movlpd xmm1,QWORD PTR ds:0x12345678 7b: 12 7c: 0f 13 0d 78 56 34 12 movlps QWORD PTR ds:0x12345678,xmm1 83: 0f 12 0d 78 56 34 12 movlps xmm1,QWORD PTR ds:0x12345678 8a: f3 0f 16 0d 78 56 34 movshdup xmm1,XMMWORD PTR ds:0x12345678 91: 12 92: f3 0f 12 0d 78 56 34 movsldup xmm1,XMMWORD PTR ds:0x12345678 99: 12 9a: f3 0f 70 0d 78 56 34 pshufhw xmm1,XMMWORD PTR ds:0x12345678,0x90 a1: 12 90 a3: f2 0f 70 0d 78 56 34 pshuflw xmm1,XMMWORD PTR ds:0x12345678,0x90 aa: 12 90 ac: 0f 60 0d 78 56 34 12 punpcklbw mm1,DWORD PTR ds:0x12345678 b3: 0f 62 0d 78 56 34 12 punpckldq mm1,DWORD PTR ds:0x12345678 ba: 0f 61 0d 78 56 34 12 punpcklwd mm1,DWORD PTR ds:0x12345678 c1: 66 0f 2e 0d 78 56 34 ucomisd xmm1,QWORD PTR ds:0x12345678 c8: 12 c9: 0f 2e 0d 78 56 34 12 ucomiss xmm1,DWORD PTR ds:0x12345678 -- Summary: objdump prints incorrect bytemodes for i386/x86_64 SIMD instructions in Intel syntax. Product: binutils Version: 2.18 (HEAD) Status: NEW Severity: normal Priority: P2 Component: binutils AssignedTo: unassigned at sources dot redhat dot com ReportedBy: ht at inter7 dot jp CC: bug-binutils at gnu dot org http://sourceware.org/bugzilla/show_bug.cgi?id=4667 ------- You are receiving this mail because: ------- You are on the CC list for the bug, or are watching someone who is. _______________________________________________ bug-binutils mailing list bug-binutils@gnu.org http://lists.gnu.org/mailman/listinfo/bug-binutils
