------- Additional Comments From fruffell at cs dot uwaterloo dot ca 2007-03-21 16:20 ------- You are wrong, 0x41 0x90 is valid instruction, and your disassembler has a bug.
Please understand the difference between the prefix 0x49 and 0x41: 0x49 -> rexB and rexW 0x41 -> rexB Therefore your instruction: 0x49 0x90 = exchange of %rax with %r8 rexB selects r8 rexW selects the full 64-bits The instruction in question: 0x41 0x90 = exchange of %eax with %r8d (bits 0-32) rexB select r8 default operand size remains at 32-bits The difference lies in the register sizes (%rax vs %eax, %r8 vs %r8d). Run the provided testcase, so that you can convince yourself that this instruction exchanges the lower 32-bits of %rax with the lower 32-bits of %rcx, and zero-extends the upper 32-bits of both registers. This is hardly a nop, as reported by your disassembler (regardless of what your assembler produces). In the future please be more thorough with your handling of bugs, as this is the second time I've been kind enough to file a detailed bug report with a testcase, only to incorrectly have it dismissed. My time is not free either, and my disassembler does not fail this testcase ;-) -- http://sourceware.org/bugzilla/show_bug.cgi?id=4218 ------- You are receiving this mail because: ------- You are on the CC list for the bug, or are watching someone who is. _______________________________________________ bug-binutils mailing list bug-binutils@gnu.org http://lists.gnu.org/mailman/listinfo/bug-binutils
