I'm curious about your next gen plans, given Phi's roadmap.


On 6/13/18 9:17 PM, Stu Midgley wrote:
low level HPC means... lots of things.  BUT we are a huge Xeon Phi shop and need low-level programmers ie. avx512, careful cache/memory management (NOT openmp/compiler vectorisation etc).

I played around with avx512 in my rzf code. https://github.com/joelandman/rzf/blob/master/avx2/rzf_avx512.c  . Never really spent a great deal of time on it, other than noting that using avx512 seemed to downclock the core a bit on Skylake.

Which dev/toolchain are you using for Phi?  I set up the MPSS bit for a customer, and it was pretty bad (2.6.32 kernel, etc.).  Flaky control plane, and a painful host->coprocessor interface.  Did you develop your own?  Definitely curious.





On Thu, Jun 14, 2018 at 1:08 AM Jonathan Engwall <engwalljonathanther...@gmail.com <mailto:engwalljonathanther...@gmail.com>> wrote:

    John Hearne wrote:
    > Stuart Midgley works for DUG?  They are currently
    > recruiting for an HPC manager in London... Interesting...

    Recruitment at DUG wants to call me about Low Level HPC. I have at
    least until 6pm.
    I am excited but also terrified. My background is C and now
    JavaScript, mostly online course work and telnet MUDs.
    Any suggestions are very much needed.
    What must a "low level HPC" know on day 1???
    Jonathan Engwall
    engwalljonathanther...@gmail.com
    <mailto:engwalljonathanther...@gmail.com>

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