On Thu, Jul 07, 2011 at 09:31:24AM -0700, Lux, Jim (337C) wrote:
> > On 07/07/2011 10:13 AM, Eugen Leitl wrote:
> > >
> > > http://www.techeye.net/chips/one-million-arm-chips-challenge-intel-bumblebee
> > >
> > > One million ARM chips challenge Intel bumblebee
> > >
> > 
> > Now say it like Dr. Evil: one MILLION processors.
> > 
> > 
> > How long is it going to take to wire them all up? And how fast are they
> > going to fail? If there's a MTBF of one million hours, that's still one
> > failure per hour.
> 
> 
> But this presents a very interesting design challenge.. when you get to this 
> sort of scale, you have to assume that at any time, some of them are going to 
> be dead or dying.  Just like google's massively parallel database engines..
> 
> It's all about ultimate scalability.  Anybody with a moderate competence 
> (certainly anyone on this list) could devise a scheme to use 1000 perfect 
> processors that never fail to do 1000 quanta of work in unit time.  It's 
> substantially more challenging to devise a scheme to do 1000 quanta of work 
> in unit time on, say, 1500 processors with a 20% failure rate.  Or even in 
> 1.2*unit time.

They do address som of that in 
ftp://ftp.cs.man.ac.uk/pub/amulet/papers/SBF_ACSD09.pdf

It's also specific to neural emulation. These should tolerate
pretty huge error rates without fouling up the qualitative
system behaviour they're trying to model.

-- 
Eugen* Leitl <a href="http://leitl.org";>leitl</a> http://leitl.org
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