Thanks, but I am not entirely clear on why the interrupts flow to
both the mlx-core driver and eth-mlx4-0.
This is what my /proc/interrupts table look like. Interrupts go to
CPU0 for mlx4_core and CPU6 for eth-mlx4-0:
4319: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-15
4320: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-14
4321: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-13
4322: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-12
4323: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-11
4324: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-10
4325: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-9
4326: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-8
4327: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-7
4328: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-6
4329: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-5
4330: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-4
4331: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-3
4332: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-2
4333: 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-1
4334: 34 0 0 0 0
34 97347 0 0 0 0
0 0 0 0 0 PCI-MSI-edge eth-
mlx4-0
4335: 3197 0 152 4 0
0 0 0 0 0 0
0 0 0 0 0 PCI-MSI-edge
mlx4_core(async)
On Oct 25, 2009, at 6:12 AM, Joachim Worringen wrote:
I assume these are MSI-X interrupts of the one Mellanox driver
instance. This feature allows to spread interrupts more or less
evenly across CPUs, in conjunction with multiple send/recv queues.
Each PCI device has a single driver (unless we talk about
virtualized I/O, which does not apply here). But a single driver
can serve any number of interrupts.
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