Lux, James P wrote:
I can't find the Intel P/E cycle, but the Ridata units are 2x10^6 (2E+6).
Is that the underlying device wearout life, or is it the apparent life at
the "integrated unit"'s external interface. For instance, if they had a
The latter I believe, as consumers (the mass market consumers) generally
don't care about the former.
wear leveler and some smart EDAC inside an ASIC that provides the interface,
and just added extra capacity to account for the life.
After all, it's not like at N cycles, the device stops working. It just
starts working "less well" and throwing more errors, and I'll guess (since I
don't have the data here in front of me) that there's a fair amount of
variability, even within a single device.
Consider the testing needed to exhaustively verify the 2E6 number.. 16GB of
512 byte sectors.. That's 160E6 sectors, roughly. They don't give an "erase
time" spec, but let's just say 1 millisecond to make things easy. So, to do
one erase on ALL sectors takes 160,000 seconds, or about 2 days.
In a mere 4 million or so days, one could actually verify the erase life.
Of course, this is why they do the statistical testing.
One can beat a single sector to death in 20,000 seconds or 6 hours. But, is
a single sector a valid test? Nope.. You KNOW the EDAC is going to get in
the way, not to mention that a single sector test doesn't address the
variability across the device issue. You'd probably want to sample, oh, 100
or 1000 or so sectors of the 160 million, to get a reasonable statistical
estimate. Now you're back in the days and weeks and months of testing (6000
hours is the better part of a year) regime.
Yup.
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