> AMD could MCM 2 shanghai chips, resulting in 6 cores (2 tri-cores) or 8
AMD socket supports 3 hypertransport channels and 2 64 bit memory busses. Somehow you would have to connect these to 2 piece of silicon. I've not heard that AMD has much MCM experience (unlike ibm and intel). Intel on the other hand had a very easy time. Intel's dual die setup was trivial in comparison, each die was designed to sit on a shared bus and the memory controller is offchip. Seems like AMD would have put in a 3rd chip into the MCM, or some how disable some functionality on one die and share the memory bus/HT from the other chip. _______________________________________________ Beowulf mailing list, Beowulf@beowulf.org To change your subscription (digest mode or unsubscribe) visit http://www.beowulf.org/mailman/listinfo/beowulf
