Lawrence Stewart <[EMAIL PROTECTED]> writes: >> On 9/3/08 10:34 AM, "Peter St. John" <[EMAIL PROTECTED]> wrote: >> >> I'm thinking that multicore will make topology interesting again, >> because of the difference between intercore on a common chip vs >> going through a nic to even the fastest fabric. >> Peter > > It is probably worth putting numbers on statements like this. For > example, a main memory reference on a fast processor these days is > around 80 nanoseconds. Sending a message to a process on another > node on a fast IB network is getting to 1.2 microseconds. > Communicating to another thread on the same socket is probably not > much faster than a memory reference since you have to thrash a > cache-line or two back and forth between cores.
Quite. It is possible that future generations of multi-core architectures will do differently, but right now, a multi-core chip looks a lot (to software) like a normal SMP setup. (I do wonder a lot whether a return to vector architectures might make more sense than multi-core -- there is at least a lot of precedent for making use of vector silicon with good compilers.) > So I am deeply skeptical of the current furor about how we need new > programming models for "multicore chips". We have models that work > perfectly well for 100-1000 core clusters, lets use them. Well, not quite. The HPC community is very good at using such things, so it isn't going to have trouble. The issue is not for people doing scientific computing, but for people doing "normal" applications. Beyond the scope of this mailing list of course. -- Perry E. Metzger [EMAIL PROTECTED] _______________________________________________ Beowulf mailing list, Beowulf@beowulf.org To change your subscription (digest mode or unsubscribe) visit http://www.beowulf.org/mailman/listinfo/beowulf
