-------------- Original message -------------- 
From: "Li, Bo" <[EMAIL PROTECTED]> 

> Intel will have CSI and on die memory controller soon following what AMD has 
> done for a few years. 
They have been talking about this (CSI) for years ... mmm ... what is the 
latest on its arrival and the details on functionality and width-by-clock 
performance envelope (I have forgotten waiting)?  The multi-core multi-socket 
revolution is happening now ... ;-) ...

> HT or CSI will help us build machines based on NUMA or similar architectures. 
> Based on current memory technologies, I can't find any methods for "memory 
> wall". And a 4 core processor can eat all memory bandwidth in some cases. 
> With 
> NUMA we can gat machines work as several current machine but connected with 
> fast 
> on-board connection. Image a super computer on desktop, and what's next? 
Yesterday's capability is todays capacity ... anything on a desktop is no 
longer a "supercomputer" ... ;-) ...

> Many-core processors are coming, how to power beowulf with them? I think it 
> is a 
> very interesting topic. 
The questions here is how large will the cores be, how long will the cross-bar 
switched interconnect scheme last on the chip, will we be able to program the 
on-chip interconnect (will we get more instuction additions to the x86-64 ISA), 
and how will on-chip memory technology change to support the many cores.

> Power 6 is a really strange processor for me. It works with a in order 
> architecture.
As a processor, it is now counter culture ... it is IBM successfully beating 
its chest and saying that we can still push up performance along the dimensions 
of increased clock and ILP (not withstanding the in order execution).
rbw

-- 

"Making predictions is hard, especially about the future." 

Niels Bohr 

-- 

Richard Walsh 
Thrashing River Consulting-- 
5605 Alameda St. 
Shoreview, MN 55126 

Phone #: 612-382-4620
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