I googled on "+raw +multicore +mesh", and found, among other things, a book chapter that went into some detail on the "Raw" prototype:

http://www.springerlink.com/index/g3u708645278lv32.pdf

(access might be limited to campuses that have agreements w/springer.)

I'm guessing that Tilera is a lot like Raw - couple generations more agressive fab, probably cleaned up design, etc. here's the Tilera guy
talking about tiled multicore streaming architectures:

http://videos.dac.com/44th/slides/42_2.ppt

From the picture in Ars Technica, there are four memory controllers for 64 processors. There is no floating point, but there would certainly be room for it in a 65 nm version.

I'm pretty sure Raw had FP, and guess Tilera does as well (not DP though.)

It seems to me that the key difficulty for building larger clusters out of these things
is the imbalance between computing and memory bandwidth.

well, I think the premise of most massively multicore is a dataflow/streaming design for programs, not a memory-based model. more recv-compute-send
rather than load-compute-store.

one very frustrating thing about Tilera is the total vapidity of their published docs. for instance, inter-tile latency, which is pretty critical in evaluating how much cache misses will hurt. heck, I'm not even clear about whether the caches implement coherency, or whether they're sw-managed.

and routing, but not so fine for general purpose computing. 16 cores per DDR interface (doesn't say if they are 64 or 128 bits wide, but I would guess 64 based on reasonable size
package pin counts) seems way too skinny a pipe to memory to be reasonable.

four DDR interfaces, which I also would guess would be a dimm wide (64b),
or something like 40 GB/s.  that really doesn't seem too terribly shabby ;)

I would be most interested in a detailed comparison of your chip, Tilera's
and just for amusement, Sun's new one ;)

regards, mark hahn.
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