An inconclusive datapoint:
The largest programs I know about (text segment size) are compiled
simulators. These things turn chip logic
into programs whose execution does whatever. RAMs aren't compiled like
this, but logic is.
For our chips, the text segment sizes are in the 20 megabyte area. Of
course our chips are small compared
to Cell or Itanium or ...
I suppose compiled simulators are a way of turning data into instructions!
Compiled simulators are also fun because they break most CPU designer's
ideas about instruction bandwidth.
They can be one huge basic block with no branches. So our 20 MB text
segment runs at about 100 simulation
cycles per second, using 2 GB/s of I stream bandwidth and the rest D
stream recording state changes.
(This is Cadence NC-Verilog, if I have this right.)
It isn't HPC exactly, but we do have several hundred CPUs running
simulation programs all the time.
-L
PS The resulting chip IS for HPC of course :-)
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