On Tue, 13 Feb 2007, Richard Walsh wrote:
To abondon von Neuman you have to abandon the cyclic re-referencing of
the same store and "store" results in-wire or along the path defined by a
code
customed data-flow processor. Them you eliminate as much of the memory
Or perhaps you have to move to
http://en.wikipedia.org/wiki/Quantum_computing
This actually moves you into an entirely different class of
computational complexity, a process that is so intrinsically parallel
that it is actually quite difficult and immensely expensive to express
it serially!
Just for the fun of it, mind you. Although there are definitely plenty
of people working on this very hard, and I'm guessing that we'll start
seeing this within 1-2 decades if not sooner. Not every problem maps
well into it, but the ones that do...
rgb
reference latency as possible. The problem/question is how much of the
given applications kernel can you swallow on a single chip before having to
got back to some kind of general memory for data or instructions. I like the
idea
of an array of FPGA cores on a chip (super-FPGA model). Less wasted
hardware. In some sense, these super, multi-mini-core designs are another
ASIC hammer looking for a nail. Fixed instruction architectures ultimately
waste hardware. Why not program the processor instead of instructions
for a predefined one-size fits all ASIC?
But I suppose the industry has to get there somehow ... and super-multi-mini
core is one way. The RAW processor already mapped out the benefits of
this approach, but I think they are just a mile post on the way to a super
FPGA
model. I think every one should be learning to program in Mitrion-C ... ;-).
rbw
--
Robert G. Brown http://www.phy.duke.edu/~rgb/
Duke University Dept. of Physics, Box 90305
Durham, N.C. 27708-0305
Phone: 1-919-660-2567 Fax: 919-660-2525 email:[EMAIL PROTECTED]
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