This is a further fix for previous commit: 6b44815b3519e0b65240991e9f12879b2b63389a the previous commit un-intentionally place the code under "if (it != allocatedFlags.end())", in fact, no matter the condition is true or false, we should both do like this.
Signed-off-by: Ruiling Song <[email protected]> --- backend/src/backend/gen_reg_allocation.cpp | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp index 6dd570d..68b7a85 100644 --- a/backend/src/backend/gen_reg_allocation.cpp +++ b/backend/src/backend/gen_reg_allocation.cpp @@ -599,6 +599,14 @@ namespace gbe // is called a "conditional modifier"). The other instructions just read // it if (insn.state.physicalFlag == 0) { + // SEL.bool instruction, the dst register should be stored in GRF + // the pred flag is used by flag register + if (insn.opcode == SEL_OP_SEL) { + ir::Register dst = insn.dst(0).reg(); + if (ctx.sel->getRegisterFamily(dst) == ir::FAMILY_BOOL && + allocatedFlags.find(dst) != allocatedFlags.end()) + allocatedFlags.erase(dst); + } auto it = allocatedFlags.find(ir::Register(insn.state.flagIndex)); if (it != allocatedFlags.end()) { insn.state.physicalFlag = 1; @@ -619,11 +627,6 @@ namespace gbe } insn.extra.function = GEN_CONDITIONAL_NEQ; } - // SEL.bool instruction, the dst register should be stored in GRF - // the pred flag is used by flag register - if (insn.opcode == SEL_OP_SEL && ctx.sel->getRegisterFamily(insn.dst(0).reg()) == ir::FAMILY_BOOL) { - allocatedFlags.erase(insn.dst(0).reg()); - } // If this is an external bool, we need to validate it if it is not validated yet. if ((insn.state.externFlag && insn.state.predicate != GEN_PREDICATE_NONE)) -- 2.4.1 _______________________________________________ Beignet mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/beignet
