From: Pan Xiuli <[email protected]> We now can get a reg as header or tmp register for send instruction or others. Also refine some old wrong attempt to get a reg.
Signed-off-by: Pan Xiuli <[email protected]> --- backend/src/backend/gen_context.cpp | 4 ++-- backend/src/backend/gen_insn_selection.cpp | 28 ++++++++++++++++++++-------- 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp index c38b7af..d872a70 100644 --- a/backend/src/backend/gen_context.cpp +++ b/backend/src/backend/gen_context.cpp @@ -3697,7 +3697,7 @@ namespace gbe uint32_t type = ra->genReg(insn.src(1)).type; uint32_t typesize = typeSize(type); const uint32_t vec_size = insn.extra.elem; - const GenRegister tmp = GenRegister::offset(header, 1); + const GenRegister tmp = GenRegister::retype(ra->genReg(insn.dst(1)), GEN_TYPE_UD); const GenRegister addr = GenRegister::toUniform(addrreg, addrreg.type); GenRegister headeraddr; bool isA64 = insn.getbti() == 255; @@ -3921,7 +3921,7 @@ namespace gbe const GenRegister coordx = GenRegister::toUniform(ra->genReg(insn.src(0)), GEN_TYPE_D); const GenRegister coordy = GenRegister::toUniform(ra->genReg(insn.src(1)), GEN_TYPE_D); const GenRegister header = GenRegister::retype(ra->genReg(insn.dst(0)), GEN_TYPE_UD); - const GenRegister tmp = GenRegister::offset(header, 1); + const GenRegister tmp = GenRegister::retype(ra->genReg(insn.dst(1)), GEN_TYPE_UD); GenRegister offsetx, offsety, blocksizereg; size_t vec_size = insn.extra.elem; uint32_t type = ra->genReg(insn.src(2)).type; diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index c14e0bc..ae523b0 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -432,6 +432,8 @@ namespace gbe SelectionInstruction *create(SelectionOpcode, uint32_t dstNum, uint32_t srcNum); /*! Return the selection register from the GenIR one */ GenRegister selReg(ir::Register, ir::Type type = ir::TYPE_FLOAT) const; + /*! Return one REG for tmp and header. */ + GenRegister selReg(void); /*! Compute the nth register part when using SIMD8 with Qn (n in 2,3,4) */ GenRegister selRegQn(ir::Register, uint32_t quarter, ir::Type type = ir::TYPE_FLOAT) const; /*! Size of the stack (should be large enough) */ @@ -1201,6 +1203,16 @@ namespace gbe #undef SEL_REG + GenRegister Selection::Opaque::selReg(void) { + const uint32_t simdWidth = ctx.getSimdWidth(); + if (simdWidth == 8) + return GenRegister::retype(GenRegister::f8grf(reg(ir::FAMILY_DWORD)), GEN_TYPE_UD); + else if (simdWidth == 16) + return GenRegister::retype(GenRegister::f8grf(reg(ir::FAMILY_WORD)), GEN_TYPE_UD); + GBE_ASSERT(false); + return GenRegister(); + } + GenRegister Selection::Opaque::selRegQn(ir::Register reg, uint32_t q, ir::Type type) const { GenRegister sreg = this->selReg(reg, type); sreg.quarter = q; @@ -4675,7 +4687,7 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp const uint32_t simdWidth = sel.ctx.getSimdWidth(); const Type type = insn.getValueType(); const uint32_t typeSize = type == TYPE_U32 ? 4 : 2; - const GenRegister header = GenRegister::retype(GenRegister::f8grf(sel.reg(FAMILY_DWORD)), GEN_TYPE_UD); + const GenRegister header = sel.selReg(); vector<GenRegister> valuesVec; for(uint32_t i = 0; i < vec_size; i++) valuesVec.push_back(sel.selReg(insn.getValue(i), type)); @@ -4685,7 +4697,7 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp tmp_size = tmp_size > 4 ? 4 : tmp_size; vector<GenRegister> tmpVec; for(uint32_t i = 0; i < tmp_size; i++) - tmpVec.push_back(GenRegister::retype(GenRegister::f8grf(sel.reg(FAMILY_DWORD)), GEN_TYPE_UD)); + tmpVec.push_back(sel.selReg()); sel.OBREAD(&valuesVec[0], vec_size, address, header, SI, &tmpVec[0], tmp_size); } @@ -5121,7 +5133,7 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp const uint32_t simdWidth = sel.ctx.getSimdWidth(); const Type type = insn.getValueType(); const uint32_t typeSize = type == TYPE_U32 ? 4 : 2; - const GenRegister header = GenRegister::retype(GenRegister::f8grf(sel.reg(FAMILY_DWORD)), GEN_TYPE_UD); + const GenRegister header = sel.selReg(); vector<GenRegister> valuesVec; for(uint32_t i = 0; i < vec_size; i++) valuesVec.push_back(sel.selReg(insn.getValue(i), type)); @@ -5131,7 +5143,7 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp tmp_size = tmp_size > 4 ? 4 : tmp_size; vector<GenRegister> tmpVec; for(uint32_t i = 0; i < tmp_size; i++) - tmpVec.push_back(GenRegister::retype(GenRegister::f8grf(sel.reg(FAMILY_DWORD)), GEN_TYPE_UD)); + tmpVec.push_back(sel.selReg()); sel.OBWRITE(address, &valuesVec[0], vec_size, header, SI, &tmpVec[0], tmp_size); } @@ -7614,11 +7626,11 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp for (uint32_t i = 0; i < vec_size; ++i) { valuesVec.push_back(sel.selReg(insn.getDst(i), type)); if(simdWidth == 16) - tmpVec.push_back(GenRegister::retype(GenRegister::f8grf(sel.reg(FAMILY_DWORD)), GEN_TYPE_UD)); + tmpVec.push_back(sel.selReg()); } const GenRegister coordx = sel.selReg(insn.getSrc(0), TYPE_U32); const GenRegister coordy = sel.selReg(insn.getSrc(1), TYPE_U32); - const GenRegister header = GenRegister::retype(GenRegister::f8grf(sel.reg(FAMILY_DWORD)), GEN_TYPE_UD); + const GenRegister header = sel.selReg(); GenRegister *tmp = NULL; if(simdWidth == 16) tmp = &tmpVec[0]; @@ -7643,9 +7655,9 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp for(uint32_t i = 0; i < vec_size; i++) { valuesVec.push_back(sel.selReg(insn.getSrc(2 + i), type)); - tmpVec.push_back(GenRegister::retype(GenRegister::f8grf(sel.reg(FAMILY_DWORD)), GEN_TYPE_UD)); + tmpVec.push_back(sel.selReg()); } - const GenRegister header = GenRegister::retype(GenRegister::f8grf(sel.reg(FAMILY_DWORD)), GEN_TYPE_UD); + const GenRegister header = sel.selReg(); sel.MBWRITE(coordx, coordy, &valuesVec[0], header, &tmpVec[0], insn.getImageIndex(), vec_size); return true; } -- 2.7.4 _______________________________________________ Beignet mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/beignet
