On Tue, Mar 10, 2015 at 2:19 AM, Zhigang Gong <[email protected]> wrote: > 2. The double support is not fully supported. For example, all the math > functions and even the divide instruction is not supported.
You're right that the hardware doesn't natively do most of the math operations on doubles (it even doesn't do floor/ceil/trunc!), but this BSpec page [0] does describe using features new to Broadwell to get IEEE-compliant fdiv and sqrt for both single-precision and double-precision. It uses the new INVM and RSQRTM math operations, the new MADM instruction, and the additional accumulator registers. It seems that INVM/RSQRTM always write the flag register (the math.eo.f0 apparently means "early out", it only seems to be documented in passing on that page) in order to skip some instructions when not necessary. [0] 3D-Media-GPGPU Engine > EU Overview > ISA Introduction > Instruction Set Reference > EUISA Instructions > math – Extended Math Function [SNB+] _______________________________________________ Beignet mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/beignet
