From: Junyan He <[email protected]> We split the load imm 64 into int64 and uint64.
Signed-off-by: Junyan He <[email protected]> --- backend/src/backend/gen_context.cpp | 2 +- backend/src/backend/gen_encoder.cpp | 4 ++-- backend/src/backend/gen_encoder.hpp | 2 +- backend/src/backend/gen_insn_selection.cpp | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp index 3fab9c8..fdada49 100644 --- a/backend/src/backend/gen_context.cpp +++ b/backend/src/backend/gen_context.cpp @@ -213,7 +213,7 @@ namespace gbe case SEL_OP_RNDZ: p->RNDZ(dst, src); break; case SEL_OP_F16TO32: p->F16TO32(dst, src); break; case SEL_OP_F32TO16: p->F32TO16(dst, src); break; - case SEL_OP_LOAD_INT64_IMM: p->LOAD_INT64_IMM(dst, src.value.i64); break; + case SEL_OP_LOAD_INT64_IMM: p->LOAD_INT64_IMM(dst, src); break; case SEL_OP_CONVI64_TO_I: { p->MOV(dst, src.bottom_half()); diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp index ba10d81..d21bece 100644 --- a/backend/src/backend/gen_encoder.cpp +++ b/backend/src/backend/gen_encoder.cpp @@ -669,8 +669,8 @@ namespace gbe pop(); } - void GenEncoder::LOAD_INT64_IMM(GenRegister dest, int64_t value) { - GenRegister u0 = GenRegister::immd((int)value), u1 = GenRegister::immd(value >> 32); + void GenEncoder::LOAD_INT64_IMM(GenRegister dest, GenRegister value) { + GenRegister u0 = GenRegister::immd((int)value.value.i64), u1 = GenRegister::immd(value.value.i64 >> 32); MOV(dest.bottom_half(), u0); MOV(dest.top_half(this->simdWidth), u1); } diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp index 9343581..97d6258 100644 --- a/backend/src/backend/gen_encoder.hpp +++ b/backend/src/backend/gen_encoder.hpp @@ -139,7 +139,7 @@ namespace gbe virtual int getDoubleExecWidth(void) = 0; virtual void MOV_DF(GenRegister dest, GenRegister src0, GenRegister tmp = GenRegister::null()); virtual void LOAD_DF_IMM(GenRegister dest, GenRegister tmp, double value); - void LOAD_INT64_IMM(GenRegister dest, int64_t value); + virtual void LOAD_INT64_IMM(GenRegister dest, GenRegister value); /*! Barrier message (to synchronize threads of a workgroup) */ void BARRIER(GenRegister src); /*! Memory fence message (to order loads and stores between threads) */ diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 5e733ac..bf3613d 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -2790,7 +2790,7 @@ namespace gbe case TYPE_S8: sel.MOV(dst, GenRegister::immw(imm.getIntegerValue())); break; case TYPE_DOUBLE: sel.LOAD_DF_IMM(dst, GenRegister::immdf(imm.getDoubleValue()), sel.selReg(sel.reg(FAMILY_QWORD), TYPE_U64)); break; case TYPE_S64: sel.LOAD_INT64_IMM(dst, GenRegister::immint64(imm.getIntegerValue())); break; - case TYPE_U64: sel.LOAD_INT64_IMM(dst, GenRegister::immint64(imm.getIntegerValue())); break; + case TYPE_U64: sel.LOAD_INT64_IMM(dst, GenRegister::immuint64(imm.getIntegerValue())); break; default: NOT_SUPPORTED; } sel.pop(); -- 1.9.1 _______________________________________________ Beignet mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/beignet
