Current selection vector handling requires the dst/src vector is starting at dst(0) or src(0).
v2: fix an assertion. v3: fix a bug in gen_context. Signed-off-by: Zhigang Gong <[email protected]> --- backend/src/backend/gen_context.cpp | 6 +++--- backend/src/backend/gen_insn_selection.cpp | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp index 351bf8e..a9b00e9 100644 --- a/backend/src/backend/gen_context.cpp +++ b/backend/src/backend/gen_context.cpp @@ -1721,9 +1721,9 @@ namespace gbe void GenContext::emitRead64Instruction(const SelectionInstruction &insn) { const uint32_t elemNum = insn.extra.elem; const uint32_t tmpRegSize = (p->curr.execWidth == 8) ? elemNum * 2 : elemNum; - const GenRegister tempAddr = ra->genReg(insn.dst(0)); - const GenRegister dst = ra->genReg(insn.dst(tmpRegSize + 1)); - const GenRegister tmp = ra->genReg(insn.dst(1)); + const GenRegister tempAddr = ra->genReg(insn.dst(tmpRegSize + 1)); + const GenRegister dst = ra->genReg(insn.dst(tmpRegSize)); + const GenRegister tmp = ra->genReg(insn.dst(0)); const GenRegister src = ra->genReg(insn.src(0)); const uint32_t bti = insn.extra.function; p->READ64(dst, tmp, tempAddr, src, bti, elemNum); diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 53038b2..fc8f1b1 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -975,11 +975,11 @@ namespace gbe SelectionVector *srcVector = this->appendVector(); SelectionVector *dstVector = this->appendVector(); - /* temporary addr register is to be modified, set it to dst registers.*/ - insn->dst(0) = tempAddr; // Regular instruction to encode for (uint32_t elemID = 0; elemID < elemNum; ++elemID) - insn->dst(elemID + 1) = dst[elemID]; + insn->dst(elemID) = dst[elemID]; + /* temporary addr register is to be modified, set it to dst registers.*/ + insn->dst(elemNum) = tempAddr; insn->src(0) = addr; insn->extra.function = bti; insn->extra.elem = valueNum; @@ -987,7 +987,7 @@ namespace gbe // Only the temporary registers need contiguous allocation dstVector->regNum = elemNum - valueNum; dstVector->isSrc = 0; - dstVector->reg = &insn->dst(1); + dstVector->reg = &insn->dst(0); // Source cannot be scalar (yet) srcVector->regNum = 1; -- 1.7.9.5 _______________________________________________ Beignet mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/beignet
