LGTM, thanks. -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Homer Hsing Sent: Monday, November 04, 2013 10:14 AM To: [email protected] Subject: [Beignet] [PATCH] fix ASR operator for 64bit integer
if operand is positive, then pad zero at high 32 bit. Signed-off-by: Homer Hsing <[email protected]> --- backend/src/backend/gen_context.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp index 43b3bc7..6007904 100644 --- a/backend/src/backend/gen_context.cpp +++ b/backend/src/backend/gen_context.cpp @@ -811,12 +811,13 @@ namespace gbe p->SEL(d, d, e); p->curr.predicate = GEN_PREDICATE_NONE; p->AND(a, a, GenRegister::immud(32)); + p->ASR(f, f, GenRegister::immd(31)); p->MOV(flagReg, GenRegister::immuw(0xFFFF)); p->curr.predicate = GEN_PREDICATE_NORMAL; p->curr.useFlag(flagReg.flag_nr(), flagReg.flag_subnr()); p->CMP(GEN_CONDITIONAL_Z, a, zero); p->SEL(d, d, c); - p->SEL(c, c, GenRegister::immd(-1)); + p->SEL(c, c, f); p->pop(); storeBottomHalf(dest, d); storeTopHalf(dest, c); -- 1.8.3.2 _______________________________________________ Beignet mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/beignet _______________________________________________ Beignet mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/beignet
