Thanks for the reply Robert! Just a quick update, today I was able to
configure some spi2 pins to interface with an ENC28J60-H development board
(SPI to Ethernet) with the following dts file:
*/dts-v1/;/plugin/;*
*#include <dt-bindings/interrupt-controller/irq.h>/** Helper to show loaded
overlays under: /proc/device-tree/chosen/overlays/*/&{/chosen} {
overlays { BONE-SPI2_0 = __TIMESTAMP__; };};/* * Update the
default pinmux of the pins. * See these files for the phandles (&P9_* &
&P8_*) *
BeagleBoard-DeviceTrees/v4.19.x-ti-overlays/src/arm/am335x-bone-common-univ.dtsi
*
BeagleBoard-DeviceTrees/v4.19.x-ti-overlays/src/arm/am572x-bone-common-univ.dtsi
*/&ocp
{ P9_17_pinmux { pinctrl-0 = <&P9_17_spi_cs_pin>; }; /* CS0 */
//P9_23_pinmux { pinctrl-0 = <&P9_23_spi_cs_pin>; }; /* CS1 */
P9_21_pinmux { pinctrl-0 = <&P9_21_spi_pin>; }; /* MOSI */ P9_18_pinmux
{ pinctrl-0 = <&P9_18_spi_pin>; }; /* MISO */ P9_22_pinmux {
pinctrl-0 = <&P9_22_spi_sclk_pin>; }; /* CLK */ P8_07_pinmux {status =
"disabled";}; /* gpios reserved for RESET and INTERRUPT pins */
P8_09_pinmux {status = "disabled";}; P8_08_pinmux {status =
"disabled";}; P8_10_pinmux {status = "disabled";};};/* * See these files
for the phandles (&bone_*) and other bone bus nodes *
BeagleBoard-DeviceTrees/v4.19.x-ti-overlays/src/arm/bbai-bone-buses.dtsi *
BeagleBoard-DeviceTrees/v4.19.x-ti-overlays/src/arm/bbb-bone-buses.dtsi
*/&bone_spi_0{
status = "okay"; #address-cells = <1>; #size-cells = <0>;
channel@0 { reg = <0>; compatible =
"microchip,enc28j60"; pinctrl-names = "default"; pinctrl-0 =
<&P8_09_default_pin>, <&P8_07_gpio_pin> ; //reg =
<0x0>; /* Use chip select 0 */
interrupt-parent = <&gpio6>; /* Interrupt on GPIO6[18] */
interrupts = <18 IRQ_TYPE_EDGE_FALLING>; symlink = "bone/spi/2.0";
spi-max-frequency = <16000000>; //spi-cpha; };};*
I still need to make use of the CS1 pin mode on P9_23. However, I see in
*BeagleBoard-DeviceTrees/v4.19.x-ti-overlays/src/arm/am572x-bone-common-univ.dtsi,*
there is no entry for *P9_23_spi_cs_pin. *I tried adding the following
lines to the bone-common-univ.dtsi:
* P9_23_spi_cs_pin: pinmux_P9_23_spi_cs_pin { pinctrl-single,pins =
< P9_23( PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3)>; }; /*
spi2_cs1.spi2_cs1, mcasp1_axr1.off */*
But even after a make clean, make all, the resulting dtbo will brick my
device..
I was wondering if you had any pointers/ideas as to how I could make this
work? Eventually, I would like to run both channels with different
interrupt,chip select and rest pins as defined above.
Thanks again,
Doug
On Wednesday, October 7, 2020 at 2:51:22 PM UTC-4 RobertCNelson wrote:
> On Wed, Oct 7, 2020 at 11:40 AM Douglas Conover
> <[email protected]> wrote:
> >
> > Hi! Thanks for this update! I've been playing around in the device trees
> for a little while in the AI, basing myself on the
> ``am5729-beagleboneai-roboticscape.dts`` and the v4.14 kernel iot image. I
> have a hardware application that requires me to use two ENC28J60 ethernet
> adapters and the SPI 2 pins (I need two chip selects and due to potential
> pin conflicts I need to use SPI2). After struggling with the v4.14
> kernel/image, I decided to try upgrading to the 4.19 kernel/image provided
> in this discussion. I was wondering if this was possible by modifying some
> of the overlay files provided in:
> >
> >
> https://github.com/beagleboard/BeagleBoard-DeviceTrees/tree/v4.19.x-ti-overlays/src/arm/overlays
> >
> > Inspecting
> ``BeagleBoard-DeviceTrees/v4.19.x-ti-overlays/src/arm/bbai-bone-buses.dtsi``,
> I could only find the bone_spi_0 and bone_spi_1 groups. Does anyone have
> any pointers on enabling spi2?
>
> Here is the mapping:
>
>
> https://github.com/beagleboard/BeagleBoard-DeviceTrees/blob/v4.19.x-ti-overlays/src/arm/bbai-bone-buses.dtsi#L413-L420
>
> Regards,
>
> --
> Robert Nelson
> https://rcn-ee.com/
>
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