Hi TJF, I increase the external RAM at startup:
https://groups.google.com/forum/#!msg/beagleboard/_8Ld1deXhSY/gAoPN2FaDwAJ (Brian B's post) I set it at the maximum size for the moment although it can be a little smaller indeed.... I forgot to make it smaller in my example. I think it is not important for the resolution issue though. Starting the outer loop at 0 wil only lead to printing the step cycle one compleet cycle earlier (from the start) but does not change the resolution either. Where do I fail to catch an error message? So any clue on the resolution issue except for impedance? Why does it only play up in rb-mode and not in single shot? Did you try the rb-mode example? I tried to use delays in setstep but at high speed you cannot use too much. It seems that delays help the issue a little but it is not useable in practice. It is also unclear what unit is used for sample delay. Are those ADC clock pulses? Then I would expect 4 clock pulses to be enough to do 4 extra ADC steps... The documentation also mentions a status bit that is used to indicate that the ADC is busy converting (page 1828). Is the status bit information used in the rb-mode? I did not try yet whether the freebasic example yields the same result. Would you recommend checking it? Best, Hans. -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/03ccd569-9d08-484e-8519-9f8f2991fe4b%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
